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ADC084S101CIMM Fiches technique(PDF) 7 Page - Texas Instruments |
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ADC084S101CIMM Fiches technique(HTML) 7 Page - Texas Instruments |
7 / 27 page tCSU tCLH SCLK CS SCLK tCONVERT tACQ tCL tACC tEN Z3 Z2 Z1 Z0 DB6 DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC DB7 DB5 DB4 DB0 16 8 7 6 5 4 3 2 1 DIN DOUT SCLK CS tDIS Zero Zero DB1 15 14 13 Tri-State Zero Zero 12 11 tCH tH tSU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 Track Hold Power Up Track Hold b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 9 10 DB5 DB4 DB3 DB2 DB1 DB0 DB5 DB4 DB3 DIN DOUT Power Up SCLK CS Power Down Control register Control register DB7 DB6 DB7 DB6 ADC084S101 www.ti.com SNAS285D – APRIL 2005 – REVISED MARCH 2013 Timing Diagrams Figure 2. ADC084S101 Operational Timing Diagram Figure 3. Timing Test Circuit Figure 4. ADC084S101 Serial Timing Diagram Figure 5. SCLK and CS Timing Parameters Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADC084S101 |
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