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AMC001CFLKA Fiches technique(PDF) 8 Page - Advanced Micro Devices

No de pièce AMC001CFLKA
Description  1, 2, 4, or 10 Megabyte 5.0 V-only Flash Memory PC Card
Download  42 Pages
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Fabricant  AMD [Advanced Micro Devices]
Site Internet  http://www.amd.com
Logo AMD - Advanced Micro Devices

AMC001CFLKA Fiches technique(HTML) 8 Page - Advanced Micro Devices

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5/4/98
Byte-Wide Operations
Byte-wide data is available on D0–D7 for read and write
operations (CE1 = low, CE2 = high). Even and odd
bytes are stored in separate memory segments (i.e.,
S0 and S1) and are accessed when A0 is low and high
respectively. The even byte is the low order byte and
the odd byte is the high order byte of a 16-bit word.
Erase operations in the byte-wide mode must account
for data multiplexing on D0–D7 by changing the state of
A0. Each memory sector or memory segment pair
must be addressed separately for erase operations.
Card Detection
Each CD (output) pin should be read by the host sys-
tem to determine if the memory card is adequately
seated in the socket. CD1 and CD2 are internally tied
to ground. If both bits are not detected, the system
should indicate that the card must be reinserted.
Write Protection
The AMD Flash memory card has three types of write
protection. The PCMCIA/JEIDA socket itself provides
the first type of write protection. Power supply and con-
trol pins have specific pin lengths in order to protect the
card with proper power supply sequencing in the case
of hot insertion and removal.
A mechanical write protect switch provides a second
type of write protection. When this switch is activated,
WE is internally forced high. The Flash memory com-
mand register is disabled from accepting any write
commands.
The third type of write protection is achieved with VCC1
and VCC2 below VLKO. Each Flash memory device that
comprises a Flash memory segment will reset the com-
mand register to the read-only mode when VCC is
below VLKO. VLKO is the voltage below which write op-
erations to individual command registers are disabled.
MEMORY CARD BUS OPERATIONS
Read Enable
Two Card Enable (CE) pins are available on the mem-
or y card. Both CE pins must be active low for
word-wide read accesses. Only one CE is required for
byte-wide accesses. The CE pins control the selection
and gates power to the high and low memory seg-
ments. The Output Enable (OE) controls gating ac-
cessed data from the memory segment outputs.
The device will automatically power-up in the read/
reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read
cycles will retrieve array data. This default value en-
sures that no spurious alteration of the memory content
occurs during the power transition. Refer to the AC
Read Characteristics and Waveforms for the specific
timing parameters.
Output Disable
Data outputs from the card are disabled when OE is at
a logic-high level. Under this condition, outputs are in
the high-impedance state.
Standby Operations
Byte-wide read accesses only require half of the read/
write output buffer (x16) to be active. In addition, only
one memory segment is active within either the high
order or low order bank. Activation of the appropriate
half of the output buffer is controlled by the combination
of both CE pins. The CE pins also control power to the
high and low-order banks of memory. Outputs of the
memory bank not selected are placed in the high im-
pedance state. The individual memory segment is acti-
vated by the address decoders. The other memory
segments operate in standby. An active memory seg-
ment continues to draw power until completion of a
write or erase operation if the card is deselected in the
process of one of these operations.
Auto Select Operation
A host system or external card reader/writer can deter-
mine the on-card manufacturer and device I.D. codes.
Codes are available after writing the 90H command to
the command register of a memory segment per
Tables 3 and 4. Reading from address location 00000H
in any segment provides the manufacturer I.D. while
address location 00002H provides the device I.D.
To terminate the Auto Select operation, it is necessary
to write the Read/Reset command sequence into the
register.
Write Operations
Write and erase operations are valid only when VCC1
and VCC2 are above 4.75 V. This activates the state
machine of an addressed memory segment. The com-
mand register is a latch which saves address, com-
mands, and data information used by the state
machine and memory array.
When Write Enable (WE) and appropriate CE(s) are at
a logic-level low, and Output Enable (OE) is at a
logic-high, the command register is enabled for write
operations. The falling edge of WE latches address in-
formation and the rising edge latches data/command
information.
Write or erase operations are performed by writing ap-
propriate data patterns to the command register of ac-
cessed Flash memory sectors or memory segments.
The byte-wide and word-wide commands are defined
in Tables 3, 4, and 5, respectively.


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