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AD7847BN Fiches technique(PDF) 2 Page - Analog Devices |
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AD7847BN Fiches technique(HTML) 2 Page - Analog Devices |
2 / 12 page REV. C –2– AD7837/AD7847–SPECIFICATIONS1 (V DD = +15 V 5%, VSS = –15 V 5%, AGNDA = AGNDB = DGND = O V. VREFA = VREFB = +10 V, RL = 2 k , CL = 100 pF [VOUT connected to RFB AD7837]. All specifications TMIN to TMAX unless otherwise noted.) Parameter A Version B Version S Version Units Test Conditions/Comments STATIC PERFORMANCE Resolution 12 12 12 Bits Relative Accuracy 2 ±1 ±1/2 ±1 LSB max Differential Nonlinearity 2 ±1 ±1 ±1 LSB max Guaranteed Monotonic Zero Code Offset Error2 @ +25 °C ±2 ±2 ±2 mV max DAC Latch Loaded with All 0s TMIN to TMAX ±4 ±3 ±4 mV max Temperature Coefficient = ±5 µV/°C typ Gain Error2 @ +25 °C ±4 ±2 ±4 LSB max DAC Latch Loaded with All 1s TMIN to TMAX ±5 ±3 ±5 LSB max Temperature Coefficient = ±2 ppm of FSR/ °C typ REFERENCE INPUTS VREF Input Resistance 8/13 8/13 8/13 k Ω min/max Typical Input Resistance = 10 k Ω VREFA, VREFB Resistance Matching ±2 ±2 ±2 % max Typically ±0.25% DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 0.8 V max Input Current ±1 ±1 ±1 µA max Digital Inputs at 0 V and VDD Input Capacitance 3 8 8 8 pF max ANALOG OUTPUTS DC Output Impedance 0.2 0.2 0.2 Ω typ Short Circuit Current 11 11 11 mA typ VOUT Connected to AGND POWER REQUIREMENTS 4 VDD Range 14.25/15.75 14.25/15.75 14.25/15.75 V min/max VSS Range –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 V min/max Power Supply Rejection ∆Gain/∆VDD ±0.01 ±0.01 ±0.01 % per % max VDD = 15 V ± 5%, VREF = –10 V ∆Gain/∆V SS ±0.01 ±0.01 ±0.01 % per % max VSS = –15 V ± 5%, V REF = +10 V IDD 8 8 8 mA max Outputs Unloaded. Inputs at Thresholds. Typically 5 mA ISS 6 6 6 mA max Outputs Unloaded. Inputs at Thresholds. Typically 3 mA AC CHARACTERISTICS 2, 3 Voltage Output Settling Time 3 3 3 µs typ Settling Time to Within ±1/2 LSB of Final 55 5 µs max Value. DAC Latch Alternately Loaded with All 0s and All 1s Slew Rate 11 11 11 V/ µs typ Digital-to-Analog Glitch Impulse 10 10 10 nV secs typ 1 LSB Change Around Major Carry Channel-to-Channel Isolation VREFA to VOUTB –95 –95 –95 dB typ VREFA = 20 V p-p, 10 kHz Sine Wave. DAC Latches Loaded with All 0s VREFB to VOUTA –95 –95 –95 dB typ VREFB = 20 V p-p, 10 kHz Sine Wave. DAC Latches Loaded with All 0s Multiplying Feedthrough Error –90 –90 –90 dB typ VREF = 20 V p-p, 10 kHz Sine Wave. DAC Latch Loaded with All 0s Unity Gain Small Signal BW 750 750 750 kHz typ VREF = 100 mV p-p Sine Wave. DAC Latch Loaded with All 1s Full Power BW 175 175 175 kHz typ VREF = 20 V p-p Sine Wave. DAC Latch Loaded with All 1s Total Harmonic Distortion –88 –88 –88 dB typ VREF = 6 V rms, 1 kHz. DAC Latch Loaded with All 1s Digital Crosstalk 1 1 1 nV secs typ Code Transition from All 0s to All 1s and Vice Versa Output Noise Voltage @ +25 °C See Typical Performance Graphs (0.1 Hz to 10 Hz) 2 2 2 µV rms typ Amplifier Noise and Johnson Noise of RFB Digital Feedthrough 1 1 1 nV secs typ NOTES 1Temperature ranges are as follows: A, B Versions, –40 °C to +85°C; S Version, –55°C to +125°C. 2See Terminology. 3Guaranteed by design and characterization, not production tested. 4The Devices are functional with V DD/VSS = ± 12 V (See typical performance graphs.). Specifications subject to change without notice. |
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