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74LVC821ADB Fiches technique(PDF) 8 Page - NXP Semiconductors

No de pièce 74LVC821ADB
Description  10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

74LVC821ADB Fiches technique(HTML) 8 Page - NXP Semiconductors

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74LVC821A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 23 November 2012
8 of 20
NXP Semiconductors
74LVC821A
10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25 C.
10. Dynamic characteristics
IOZ
OFF-state
output
current
VI =VIH or VIL; VCC = 3.6 V;
VO =5.5 V orGND;
-0.1
5-
20
A
IOFF
power-off
leakage
current
VCC = 0 V; VI or VO = 5.5 V
-
0.1
10
-
20
A
ICC
supply
current
VCC = 3.6 V; VI =VCC or GND;
IO =0A
-0.1
10
-40
A
I
CC
additional
supply
current
per input pin;
VCC = 2.7 V to 3.6 V;
VI =VCC  0.6 V; IO =0A
-
5
500
-
5000
A
CI
input
capacitance
VCC = 0 V to 3.6 V;
VI =GND to VCC
-
5.0
--
-pF
Table 6.
Static characteristics ...continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
tpd
propagation
delay
CP to Qn; see Figure 7
[2]
VCC = 1.2 V
-
18
-
-
-
ns
VCC = 1.65 V to 1.95 V
2.4
8.6
17.1
2.3
19.7
ns
VCC = 2.3 V to 2.7 V
1.8
4.5
8.8
1.6
10.1
ns
VCC = 2.7 V
1.5
4.1
8.5
2.2
11.0
ns
VCC = 3.0 V to 3.6 V
1.5
3.8
7.3
2.0
9.5
ns
ten
enable time
OE to Qn; see Figure 9
[2]
VCC = 1.2 V
-
20
-
-
-
ns
VCC = 1.65 V
1.8
7.7
17.4
1.6
20.1
ns
VCC = 2.3 V to 2.7 V
1.5
4.3
9.6
1.3
11.0
ns
VCC = 2.7 V
1.3
4.4
8.8
2.4
11.0
ns
VCC = 3.0 V to 3.6 V
1.5
3.5
7.6
1.5
9.5
ns
tdis
disable time
OE to Qn; see Figure 9
[2]
VCC = 1.2 V
-
9.0
-
-
-
ns
VCC = 1.65 V
2.5
4.4
10.4
1.8
12.0
ns
VCC = 2.3 V to 2.7 V
1.0
2.4
5.9
0.6
6.8
ns
VCC = 2.7 V
1.5
3.3
6.8
2.2
8.5
ns
VCC = 3.0 V to 3.6 V
1.5
3.0
6.2
1.9
8.0
ns


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