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74AUP1GU04 Fiches technique(PDF) 1 Page - NXP Semiconductors |
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74AUP1GU04 Fiches technique(HTML) 1 Page - NXP Semiconductors |
1 / 21 page 1. General description The 74AUP1GU04 provides the single unbuffered inverting gate. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption; ICC = 0.9 A (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information 74AUP1GU04 Low-power unbuffered inverter Rev. 5 — 29 June 2012 Product data sheet Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1GU04GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1GU04GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1.45 0.5 mm SOT886 74AUP1GU04GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1 0.5 mm SOT891 74AUP1GU04GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 1.0 0.35 mm SOT1115 74AUP1GU04GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 1.0 0.35 mm SOT1202 74AUP1GU04GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 0.8 0.35 mm SOT1226 |
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