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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD5399YRMZ Fiches technique(PDF) 3 Page - Analog Devices |
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AD5399YRMZ Fiches technique(HTML) 3 Page - Analog Devices |
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3 / 12 page  AD5399 Rev. D | Page 3 of 12 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD = 5 V ± 10%, –40°C < TA < +105°C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS Resolution N 12 Bits Differential Nonlinearity Error DNL –1 ±0.5 +1 LSB Codes 2048 to 2052, due to int. op amp offset –1.2 ±0.5 +1.2 LSB Integral Nonlinearity Error INL –0.4 ±0.02 +0.4 %FS Positive Full-Scale Error V+FSE Code = 0xF –0.75 –0.15 +0.75 %FS Bipolar Zero-Scale Error VBZSE Code = 0x000 –0.75 –0.15 +0.75 %FS Negative Full-Scale Error V–FSE Code = 0x800 –0.75 –0.15 +0.75 %FS ANALOG OUTPUTS Nominal Positive Full-Scale VOUTA/B Code = 0x7FF 4 V Positive Full-Scale Tempco2 TCVOUTA/B Code = 0x7FF, TA = 0°C to 70°C –40 ±10 +40 ppm/°C Code = 0xFF, TA = –40°C to +105°C –60 ±10 +60 ppm/°C Nominal VBZ Output Voltage VBZ 1.995 2.000 2.004 V Bipolar Zero Output Resistance2 RBZ 1 Ω VBZ Output Voltage Tempco TCVBZ TA = 0°C to 70°C –40 ±10 +40 ppm/°C TA = –40°C to +105°C –60 ±10 +60 ppm/°C Nominal Peak-to-Peak Output Swing |V+FS| + |V–FS| Code 0x7FF to Code 0x800 4 V DIGITAL INPUTS Input Logic High VIH VDD = 5 V 2.4 V Input Logic Low VIL VDD = 5 V 0.8 V Input Current IIL VIN = 0 V or 5 V, VDD = 5 V ±1 µA Input Capacitance2 CIL 5 pF POWER SUPPLIES Power Supply Range VDD RANGE 4.5 5.5 V Supply Current IDD VIH = VDD or VIL = 0 V 1.8 2.6 mA Supply Current in Shutdown IDD_SHDN VIH = VDD or VIL = 0 V, B14 = 0, TA = 0°C to 105°C 10 100 µA VIH = VDD or VIL = 0 V, B14 = 0, TA = –40°C to 0°C 100 500 µA Power Dissipation3 PDISS VIH = VDD or VIL = 0 V, VDD = 5.5 V 9 13 mW Power Supply Sensitivity PSS ∆VDD = 5 V ± 10% –0.006 +0.003 +0.006 %/% DYNAMIC CHARACTERISTICS2 Settling Time tS 0.1% error band 0.8 µs Digital Feedthrough Q 10 nV-s Bipolar Zero-Scale Glitch G 10 nV-s Capacitive Load Driving Capability CL No oscillation 1000 pF INTERFACE TIMING CHARACTERISTICS2, 4 SCLK Cycle Frequency tCYC 33 MHz SCLK Clock Cycle Time t1 30 ns Input Clock Pulse Width t2, t3 Clock level low or high 15 ns Data Setup Time t4 5 ns Data Hold Time t5 0 ns CS to SCLK Active Edge Setup Time t6 5 ns SCLK to CS Hold Time t7 0 ns Repeat Programming, CS High Time t8 30 ns 1 Typical values represent average readings at 25°C and VDD = 5 V. 2 Guaranteed by design and not subject to production test. 3 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 4 See timing diagram (Figure 5) for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using VDD = 5 V. Input logic should have a 1 V/µs minimum slew rate. |
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