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TPS40490MHRHDR Fiches technique(PDF) 7 Page - Texas Instruments

No de pièce TPS40490MHRHDR
Description  5-V to 60-V WIDE-INPUT SYNCHRONOUS PWM BUCK CONTROLLER
Download  38 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS40490MHRHDR Fiches technique(HTML) 7 Page - Texas Instruments

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TPS40490
www.ti.com
SLVSCB4 – OCTOBER 2013
THERMAL INFORMATION
TPS40490
THERMAL METRIC(1)
UNITS
RHD 28 pins
θJA
Junction-to-ambient thermal resistance(1)
36.6
θJC(top)
Junction-to-case(top) thermal resistance(2)
26.2
θJB
Junction-to-board thermal resistance(3)
8.8
°C/W
ψJT
Junction-to-top characterization parameter(4)
0.3
ψJB
Junction-to-board characterization parameter(5)
8.7
θJC(bottom)
Junction-to-case(bottom) thermal resistance(6)
1.9
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7.
(6)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 150°C, VIN = 48 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT SUPPLY
VIN
Input Voltage range
5
60
V
IDDSDN
Shutdown
VEN < 100 mV
2
µA
IDDQ
Quiescent, drivers not switching
VEN > 2 V, fSW = 1 MHz
2
mA
ENABLE
Enable pin voltage to disable the
VDIS
300
mV
device
Enable pin voltage to enable the
VEN
1200
mV
device
IEN
Enable pin source current
50
150
300
nA
VDR AND 3.3-V REGULATORS
TPS40490MLRHD: VEN ≥ 2 V, 5.6 V < VIN ≤ 60 V
4.8
Driver voltage regulator output
VDR_MOSFET
V
voltage
TPS40490MHRHD: VEN ≥ 2 V, 6.8 V < VIN ≤ 60 V
6.8
TPS40490MHRHD
6.25
Driver voltage UVLO MOSFET
VDR_MOSFET_UVLO
V
rising edge
TPS40490MLRHD
4.4
VDR_ACCURACY
Drive voltage accuracy
-4.5
4.5
%
TPS40490MHRHD
11
V
VDR_EXT_UVLO
External drive UVLO
TPS40490MLRHD
5
V
V3p3
Internal biasing supply
ILOAD = 0 to 10 mA
3.2
V
FIXED AND PROGRAMMABLE UVLO
VUVLO
Programmable UVLO ON voltage
870
900
930
mV
IUVLO
Hysteresis current out of UVLO pin
5
µA
REFERENCE
TJ = 25°C, 6 V < VVIN < 60 V
594
600
606
Reference voltage (+ input of the
VREF
–40°C
≤ TJ 125°C, 6 V < VVIN ≤ 60 V
588
600
612
mV
error amplifier)
–40°C
≤ TJ 125°C, 5 V < VVIN ≤ 60 V
576
600
624
OSCILLATOR
TPS40490MHRHD:
100
5400
VVIN = 48 V
fsw
Switching frequency range
Set by external resistor
kHz
TPS40490MLRHD:
100
5400
VVIN = 12 V
Copyright © 2013, Texas Instruments Incorporated
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