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CAT1162WI-28-GT3 Fiches technique(PDF) 9 Page - ON Semiconductor |
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CAT1162WI-28-GT3 Fiches technique(HTML) 9 Page - ON Semiconductor |
9 / 13 page CAT1161, CAT1162 http://onsemi.com 9 READ OPERATIONS The READ operation for the CAT1161/2 is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Immediate/Current Address Read The CAT1161/2 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. For all devices, N=E=2047. The counter will wrap around to Zero and continue to clock out valid data for the 16K devices. After the CAT1161/2 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8−bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Figure 9. Immediate Address Read Timing SCL SDA8TH BIT STOP NO ACK DATA OUT 8 SLAVE ADDRESS S A C K DATA N O A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T 9 Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1161/2 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT1161/2 then responds with its acknowledge and sends the 8−bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1161/2 sends the inital 8−bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. The CAT1161/2 will continue to output an 8−bit byte for each acknowledge, thus sending the STOP condition. The data being transmitted from the CAT1161/2 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT1161/2 address bits so that the entire memory array can be read during one operation. If more than E (where E=2047 for the CAT1161/2) bytes are read out, the counter will ‘wrap around’ and continue to clock out data bytes. Manual Reset Operation The CAT116x RESET or RESET pin can also be used as a manual reset input. Only the “active” edge of the manual reset input is internally sensed. The positive edge is sensed if RESET is used as a manual reset input and the negative edge is sensed if RESET is used as a manual reset input. An internal counter starts a 200 ms count. During this time, the complementary reset output will be kept in the active state. If the manual reset input is forced active for more than 200 ms, the complementary reset output will switch back to the non active state after the 200 ms expired, regardless for how long the manual reset input is forced active. The embedded EEPROM is disabled as long as a reset condition is maintained on any RESET pin. If the external forced RESET/RESET is longer than internal controlled time−out period, tPURST, the memory will not respond with an acknowledge for any access as long as the manual reset input is active. |
Numéro de pièce similaire - CAT1162WI-28-GT3 |
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Description similaire - CAT1162WI-28-GT3 |
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