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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD9446BSVZ-801 Fiches technique(PDF) 3 Page - Analog Devices |
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AD9446BSVZ-801 Fiches technique(HTML) 3 Page - Analog Devices |
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3 / 36 page  AD9446 Rev. 0 | Page 3 of 36 SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.2 V p-p differential input, internal trimmed reference (1.6 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise noted. Table 1. AD9446BSVZ-80 AD9446BSVZ-100 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION Full 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −5 ±0.1 +5 −5 ±0.1 +5 mV Gain Error Full −3 ±0.6 +3 −3 ±0.5 +3 % FSR 25°C −2 ±0.3 +2 −2 ±0.3 +2 % FSR Differential Nonlinearity (DNL)1 Full −0.75 ±0.4 +0.75 −0.85 ±0.4 +0.85 LSB Integral Nonlinearity (INL)1 25°C −5 ±3.0 +5 −6 ±3.0 +6 LSB VOLTAGE REFERENCE Output Voltage1 VREF = 1.6 V (3.2 V p-p Analog Input Range) Full 1.6 1.6 V Load Regulation @ 1.0 mA Full ±2 ±2 mV Reference Input Current (External 1.6 V Reference) Full μA INPUT REFERRED NOISE 25°C 1.5 1.9 LSB rms ANALOG INPUT Input Span VREF = 1.6 V Full 3.2 3.2 V p-p VREF = 1.0 V (External) Full 2.0 2.0 V p-p Internal Input Common-Mode Voltage Full 3.5 3.5 V External Input Common-Mode Voltage Full 3.2 3.8 3.2 3.8 V Input Resistance2 Full 1 1 kΩ Input Capacitance2 Full 6 6 pF POWER SUPPLIES Supply Voltage AVDD1 Full 3.14 3.3 3.46 3.14 3.3 3.46 V AVDD2 Full 4.75 5.0 5.25 4.75 5.0 5.25 V DRVDD—LVDS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V DRVDD—CMOS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V Supply Current IAVDD1 Full 335 365 368 401 mA IAVDD21 Full 204 234 223 255 mA IDRVDD1—LVDS Outputs Full 68 75 69 75 mA IDRVDD1—CMOS Outputs Full 14 14 mA PSRR Offset Full 1 1 mV/V Gain Full 0.2 0.2 %/V POWER CONSUMPTION LVDS Outputs Full 2.4 2.6 2.6 2.8 W CMOS Outputs (DC Input) Full 2.2 2.3 W 1 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and approximately 5 pF loading on each output bit for CMOS output mode. 2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure. |
Numéro de pièce similaire - AD9446BSVZ-801 |
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Description similaire - AD9446BSVZ-801 |
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