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SMP04ES Fiches technique(PDF) 7 Page - Analog Devices |
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SMP04ES Fiches technique(HTML) 7 Page - Analog Devices |
7 / 15 page SMP04 –7– REV. D GENERAL INFORMATION The SMP04 is a quad sample-and-hold with each track-and- hold having its own input, output, control, and on-chip hold capacitor. The combination of four high performance track-and- hold capacitors on a single chip greatly reduces board space and design time while increasing reliability. After the device selection, the primary considerations in using track-and-holds are the hold capacitor and layout. The SMP04 eliminates most of these problems by having the hold capacitors internal, eliminating the problems of leakage, feedthrough, guard ring layout and dielectric absorption. POWER SUPPLIES The SMP04 is capable of operating with either single or dual supplies over a voltage range of 7 to 15 volts. Based on the supply voltages chosen, VDD and VSS establish the output volt- age range, which is: VSS + 0.05 V ≤ VOUT ≤ VDD –2 V Note that several specifications, including acquisition time, offset and output voltage compliance will degrade for a total supply voltage of less than 7 V. Positive supply current is typi- cally 4 mA with the outputs unloaded. The SMP04 has an inter- nally regulated TTL supply so that TTL/CMOS compatibility will be maintained over the full supply range. Single Supply Operation Grounding Considerations In single supply applications, it is extremely important that the VSS (negative supply) pin be connected to a clean ground. This is because the hold capacitor is internally tied to VSS. Any noise or disturbance in the ground will directly couple to the output of the sample-and-hold, degrading the signal-to-noise performance. It is advisable that the analog and digital ground traces on the circuit board be physically separated to reduce digital switching noise from entering the analog circuitry. Power Supply Bypassing For optimum performance, the VDD supply pin must also be bypassed with a good quality, high frequency ceramic capacitor. The recommended value is 0.1 µF. In the case where dual sup- plies are used, VSS (negative supply) bypassing is particularly important. Again this is because the internal hold capacitor is tied to VSS. Good bypassing prevents high frequency noise from entering the sample-and-hold amplifier. A 0.1 µF ceramic bypass capacitor is generally sufficient. For high noise environments, adding a 10 µF tantalum capacitor in parallel with the 0.1 µF provides additional protection. Power Supply Sequencing It may be advisable to have the VDD turn on prior to having logic levels on the inputs. The SMP04 has been designed to be resis- tant to latch-up, but standard precautions should still be taken. OUTPUT BUFFERS (Pins 1, 2, 14 and 15) The buffer offset specification is ±10 mV; this is less than 1/2 LSB of an 8-bit DAC with 10 V full scale. Change in offset over the output range is typically 3 mV. The hold step is the magnitude of the voltage step caused when switching from sample-to-hold mode. This error is sometimes referred to as the pedestal error or sample-to-hold offset, and is about 2 mV with little variation. The droop rate of a held channel is 2 µV/ms typical and ±25 µV/ ms maximum. The buffers are designed primarily to drive loads connected to ground. The outputs can source more than 1.2 mA each, over the full voltage range and maintain specified accuracy. In split supply operation, symmetrical output swings can be obtained by restricting the output range to 2 V from either supply. On-chip SMP04 buffers eliminate potential stability problems associated with external buffers; outputs are stable with capaci- tive loads up to 500 pF. However, since the SMP04’s buffer outputs are not short-circuit protected, care should be taken to avoid shorting any output to the supplies or ground. SIGNAL INPUT (Pins 3, 5, 11 and 12) The signal inputs should be driven from a low impedance voltage source such as the output of an op amp. The op amp should have a high slew rate and fast settling time if the SMP04’s fast acquisition time characteristics are to be maintained. As with all CMOS devices, all input voltages should be kept within range of the supply rails (VSS ≤ VIN ≤ VDD) to avoid the possibil- ity of setting up a latch-up condition. The internal hold capacitance is typically 60 pF and the internal switch ON resistance is 2 k Ω. If single supply operation is desired, op amps such as the OP183 or AD820, that have input and output voltage compliances including ground, can be used to drive the inputs. Split sup- plies, such as ±7.5 V, can be used with the SMP04 and the above mentioned op amps. APPLICATION TIPS All unused digital inputs should be connected to logic LOW and the analog inputs connected to analog ground. For connec- tors or driven analog inputs that may become temporarily dis- connected, a resistor to VSS or analog ground should be used with a value ranging from 0.2 M Ω to 1 MΩ. Do not apply signals to the SMP04 with power off unless the input current’s value is limited to less than 10 mA. Track-and-holds are sensitive to layout and physical connections. For the best performance, the SMP04 should not be socketed. |
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