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AD9887AKS-170 Fiches technique(PDF) 11 Page - Analog Devices |
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AD9887AKS-170 Fiches technique(HTML) 11 Page - Analog Devices |
11 / 52 page AD9887A Rev. B | Page 11 of 52 PIN FUNCTION DETAILS—PINS SHARED BETWEEN DIGITAL AND ANALOG INTERFACES Sync Outputs HSOUT Horizontal Sync Output The horizontal sync output is a reconstructed version of the video Hsync, phase-aligned with DATACK. The polarity of this output can be controlled via a serial bus bit. In analog interface mode, the placement and duration are variable. In digital interface mode, the placement and duration are set by the graphics transmitter. VSOUT Vertical Sync Output The Vsync is separated from a composite signal or a direct pass-through of the Vsync input. The polarity of this output can be controlled via a serial bus bit. The placement and duration in all modes are set by the graphics transmitter. 2-Wire Serial Port SDA Serial Port Data I/O SCL Serial Port Data Clock A0 Serial Port Address Input 1 A1 Serial Port Address Input 2 For a full description of the 2-wire serial register and how it works, see the 2-Wire Serial Control Port section. Data Outputs RED A Data Output, Red Channel, Port A/Even RED B Data Output, Red Channel, Port B/Odd GREEN A Data Output, Green Channel, Port A/Even GREEN B Data Output, Green Channel, Port B/Odd BLUE A Data Output, Blue Channel, Port A/Even BLUE B Data Output, Blue Channel, Port B/Odd These outputs are the main data outputs. Bit 7 is the MSB. These outputs are shared between the two interfaces. Data Clock Outputs DATACK Data Output Clock DATACK Data Output Clock Complement Like the data outputs, the data clock outputs are shared between the two interfaces. They also behave differently, depending on which interface is active. See the Theory of Operation and Design Guide— Analog Interface and the Theory of Operation— Digital Interface sections for details on how these pins behave. Sync Detect SCDT Chip Active/Inactive Detect Output The logic for the SCDT pin is analog interface HSYNC detection or digital interface DE detection. Therefore, the SCDT pin switches to logic low under two conditions: when neither interface is active, or when the chip is in full power-down mode. The data outputs are automatically set to three-state when SCDT is low. This pin can be read by a controller to identify periods of inactivity. Scan Function SCANIN Data Input for Scan Function By using the scan function, 48 bits of data can be loaded into the data outputs. Data is input serially through this pin, clocked with the SCANCLK pin, and comes through the outputs as parallel words. This function is useful for loading known data into a graphics controller chip for testing purposes. SCANOUT Data Output for Scan Function The data input serially into the SCANIN register can be read through this pin. Data is read on a FIFO basis and is clocked via the SCANCLK pin. SCANCLK Data Clock for Scan Function This pin clocks the data for the scan function. It controls both data input and output. |
Numéro de pièce similaire - AD9887AKS-170 |
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