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74LVC2G126DCTRG4 Fiches technique(PDF) 3 Page - Texas Instruments |
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74LVC2G126DCTRG4 Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 15 page www.ti.com Recommended Operating Conditions (1) SN74LVC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES205J – APRIL 1999 – REVISED JANUARY 2007 MIN MAX UNIT Operating 1.65 5.5 VCC Supply voltage V Data retention only 1.5 VCC = 1.65 V to 1.95 V 0.65 × V CC VCC = 2.3 V to 2.7 V 1.7 VIH High-level input voltage V VCC = 3 V to 3.6 V 2 VCC = 4.5 V to 5.5 V 0.7 × V CC VCC = 1.65 V to 1.95 V 0.35 × V CC VCC = 2.3 V to 2.7 V 0.7 VIL Low-level input voltage V VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V 0.3 × V CC VI Input voltage 0 5.5 V High or low state 0 VCC VO Output voltage V 3-state 0 5.5 VCC = 1.65 V –4 VCC = 2.3 V –8 IOH High-level output current –16 mA VCC = 3 V –24 VCC = 4.5 V –32 VCC = 1.65 V 4 VCC = 2.3 V 8 IOL Low-level output current 16 mA VCC = 3 V 24 VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 ∆t/∆v Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V VCC = 5 V ± 0.5 V 5 TA Operating free-air temperature –40 85 °C (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 Submit Documentation Feedback |
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Description similaire - 74LVC2G126DCTRG4 |
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