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UC2860DW Fiches technique(PDF) 6 Page - Texas Instruments |
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UC2860DW Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 10 page UC1860 UC2860 UC3860 FAULT MANAGEMENT SECTION During UVLO, the fault management section is initialized. The latch is reset, and both Sft Strt (soft start) and Rst Dly (restart delay) are pulled low. When Sft Strt is low, it low- ers the upper clamp of the error amplifier. As Sft Strt in- creases in voltage, the upper clamp increases from a value equal to the lower clamp until it is 2V more positive. A capacitor to ground from the Sft Strt pin will control the start rate. UNCOMMITTED COMPARATOR The uncommitted comparator, biased from the reference voltage, operates independently from the rest of the chip. The open collector output is capable of sinking 2mA. The inputs are valid in the common mode range of -0.3 to 3.0V. As long as one of the inputs is within this range, the other can be as high as 5V. The high speed fault comparator will work over the input common mode range of -0.3 to 3.0V. When a fault is sensed, the one shot is immediately terminated, Sft Strt is pulled low, and Rst Dly is allowed to go high. Three modes of fault disposition can easily be implemented. If Rst Dly is externally held low, then a detected fault will shut the chip down permanently. If the Rst Dly pin is left open, a fault will simply cause an interruption of opera- tion. If a capacitor is connected from Rst Dly to ground, then hic-up operation is implemented. The hic-up time is: t (off) = 600 kohm * C(Rst Dly). Input Bias Current Input Voltage 6 |
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Description similaire - UC2860DW |
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