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TLC7528EDWR Fiches technique(PDF) 10 Page - Texas Instruments |
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TLC7528EDWR Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 27 page TLC7528C, TLC7528E, TLC7528I DUAL 8BIT MULTIPLYING DIGITALTOANALOG CONVERTERS SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION WR Address Decode Logic Address Bus Data Bus D0 − D7 DB7 DB0 WR CS DACA/DACB TLC7528 IORQ CPU Z80-A A8 − A15 A A + 1 NOTE A: A = decoded address for TLC7528 DACA A + 1 = decoded address for TLC7528 DACB 8 8 Figure 7. TLC7528 To Z-80A Interface programmable window detector The programmable window comparator shown in Figure 8 determines if the voltage applied to the DAC feedback resistors is within the limits programmed into the data latches of these devices. Input signal range depends on the reference and polarity; that is, the test input range is 0 to −Vref. The DACA and DACB data latches are programmed with the upper and lower test limits. A signal within the programmed limits drives the output high. |
Numéro de pièce similaire - TLC7528EDWR |
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Description similaire - TLC7528EDWR |
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