CDC5801A

LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH

PROGRAMMABLE DELAY AND PHASE ALIGNMENT

SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005

6

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS†

MIN

TYP‡

MAX

UNIT

Output voltage during CLK stop

mode

See Figure 1

1.1

2

V

VOX

Output crossing-point voltage

See Figure 1 and Figure 4

0.5VDDO−0.2

0.5VDDO+0.2

V

VO

Output voltage swing (VOH − VOL)

See Figure 1

1.7

2.9

V

Input clamp voltage

VDD = 3 V,

II = −18 mA

−1.2

V

VOH

High-level output voltage

See Figure 1, VDD = 3 to 3.6 V

2.0

2.6

V

VOH

High-level output voltage

VDD = 3 V,

IOH = −16 mA

2.2

V

VOL

Low-level output voltage

See Figure 1, VDD = 3 to 3.6 V

0.3

0.6

V

VOL

Low-level output voltage

VDD = 3 V,

IOL = 16 mA

0.5

V

VDD = 3.135 V,

VO = 1 V

−32

−52

IOH

High-level output current

VDD = 3.3 V,

VO = 1.65 V

−51

mA

IOH

High-level output current

VDD = 3.465 V,

VO = 3.135 V

−14.5

−21

mA

VDD = 3.135 V,

VO = 1.95 V

43

61.5

IOL

Low-level output current

VDD = 3.3 V,

VO = 1.65 V

65

mA

IOL

Low-level output current

VDD = 3.465 V,

VO = 0.4 V

25.5

36

mA

IOZ

High-impedance-state output

current

P0 = 0,

P1 = 1

±10

µA

IOZ(STOP)

High-impedance-state output

current during CLK stop

Stop = 0, VO = GND or VDD

±100

µA

IOZ(PD)

High-impedance-state output

current in power-down state

PWRDNB = 0,

VO = GND or VDD

−10

100

µA

High-level input

REFCLK,

STOPB

VDD = 3.6 V,

VI = VDD

10

IIH

High-level input

current

PWRDNB,

P0:2, MULT/

DIV0:1

VDD = 3.6 V,

VI = VDD

10

µA

Low-level input

REFCLK,

STOPB

VDD = 3.6 V,

VI = 0

−10

IIL

Low-level input

current

PWRDNB,

P0:2, MULT/

DIV0:1

VDD = 3.6 V,

VI = 0

−10

µA

ZO

Output impedance

High state

RI at IO −14.5 mA to −16.5 mA

15

35

50

Ω

ZO

Output impedance

(single ended)

Low state

RI at IO 14.5 mA to 16.5 mA

11

17

35

Ω

Reference current

VDDREF,

VDD = 3.6 V

PWRDNB = 0

50

µA

Reference current

VDDREF,

VDDPD

VDD = 3.6 V

PWRDNB = 1

0.5

mA

CI

Input capacitance

VI = VDD or GND

2

pF

CO

Output capacitance

VO = VDD or GND

3

pF

IDD(PD)

Supply current in power-down state

REFCLK = 0 MHz to 100 MHz,

PWDNB = 0,

STOPB = 1

150

µA

IDD(CLKSTOP) Supply current in CLK stop state

BUSCLK configured for 500 MHz

40

mA

IDD(NORMAL) Supply current in normal state

BUSCLK = 500 MHz

P0:2 = 000; load see Figure 1

70

mA

† VDD refers to any of the following; VDDPA, VDDPD, VDDREF, VDDO, and VDDP

‡ All typical values are at VDD = 3.3 V, TA = 25°C.