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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM3703CBP Fiches technique(PDF) 1 Page - Texas Instruments |
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AM3703CBP Fiches technique(HTML) 1 Page - Texas Instruments |
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1 / 280 page  AM3715, AM3703 www.ti.com SPRS616F – JUNE 2010 – REVISED AUGUST 2011 AM3715, AM3703 Sitara ARM Microprocessors Check for Samples: AM3715, AM3703 1 AM3715, AM3703 Sitara ARM Microprocessors 1.1 Features 123456 Pseudo-SRAM • AM3715/03 Sitara ARM Microprocessors: – Flexible Asynchronous Protocol – Compatible with OMAP™ 3 Architecture Control for Interface to Custom Logic – Sitara™ ARM® Microprocessor (MPU) (FPGA, CPLD, ASICs, etc.) Subsystem – Nonmultiplexed Address/Data Mode • Up to 1-GHz Sitara ™ ARM® Cortex™-A8 (Limited 2K-Byte Address Space) Core – 1.8-V I/O and 3.0-V (MMC1 only), Also supports 300, 600, and 800-MHz 0.9-V to 1.2-V Adaptive Processor Core operation Voltage • NEON ™ SIMD Coprocessor 0.9-V to 1.1-V Adaptive Core Logic Voltage – POWERVR SGX™ Graphics Accelerator Note: These are default Operating (AM3715 only) Performance Point (OPP) voltages and could • Tile Based Architecture Delivering up to be optimized to lower values using 20 MPoly/sec SmartReflex AVS. • Universal Scalable Shader Engine: – Commercial, Industrial, and Extended Multi-threaded Engine Incorporating Pixel Temperature Grades and Vertex Shader Functionality – Serial Communication • Industry Standard API Support: • 5 Multichannel Buffered Serial Ports OpenGLES 1.1 and 2.0, OpenVG1.0 (McBSPs) • Fine Grained Task Switching, Load – 512 Byte Transmit/Receive Buffer Balancing, and Power Management (McBSP1/3/4/5) • Programmable High Quality Image – 5K-Byte Transmit/Receive Buffer Anti-Aliasing (McBSP2) – External Memory Interfaces: – SIDETONE Core Support (McBSP2 and • SDRAM Controller (SDRC) 3 Only) For Filter, Gain, and Mix – 16, 32-bit Memory Controller With Operations 1G-Byte Total Address Space – Direct Interface to I2S and PCM Device – Interfaces to Low-Power SDRAM and T Buses – SDRAM Memory Scheduler (SMS) and – 128 Channel Transmit/Receive Mode Rotation Engine • Four Master/Slave Multichannel Serial • General Purpose Memory Controller Port Interface (McSPI) Ports (GPMC) • High-Speed/Full-Speed/Low-Speed USB – 16-bit Wide Multiplexed Address/Data OTG Subsystem (12-/8-Pin ULPI Interface) Bus • High-Speed/Full-Speed/Low-Speed – Up to 8 Chip Select Pins With Multiport USB Host Subsystem 128M-Byte Address Space per Chip – 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Select Pin Serial Interface – Glueless Interface to NOR Flash, • One HDQ/1-Wire Interface NAND Flash (With ECC Hamming • Four UARTs (One with Infrared Data Code Calculation), SRAM and Association [IrDA] and Consumer Infrared 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 POWERVR SGX is a trademark of Imagination Technologies Ltd. 3 OMAP, Sitara are trademarks of Texas Instruments. 4 Cortex, NEON are trademarks of ARM Limited. 5 ARM is a registered trademark of ARM Ltd. 6 All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2010–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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Description similaire - AM3703CBP |
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