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AM1705BPTP3 Fiches technique(PDF) 4 Page - Texas Instruments |
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AM1705BPTP3 Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 164 page Switched Central Resource (SCR) 16 KB I-Cache 16 KB D-Cache 4 KB ETB ARM926EJ-S CPU With MMU ARM Subsystem JTAG Interface System Control Input Clock(s) 64 KB ROM 8 KB RAM (Vector Table) Power/Sleep Controller Pin Multiplexing PLL/Clock Generator w/OSC General- Purpose Timer General- Purpose Timer (Watchdog) Serial Interfaces I C (2) 2 SPI (2) UART (3) Audio Ports McASP w/FIFO (2) DMA Peripherals External Memory Interfaces Connectivity EDMA3 Control Timers eHRPWM (3) eCAP (3) eQEP (2) (10/100) EMAC (RMII) MDIO USB2.0 OTG Ctlr PHY MMC/SD (8b) EMIFB SDRAM Only (16b/32b) GPIO 128 KB RAM Shared Memory EMIFA NAND/ Flash (8b) PRU Subsystem Customizable Interface Memory Protection AM1705 SPRS657D – FEBRUARY 2010 – REVISED MARCH 2013 www.ti.com 1.3 Functional Block Diagram Figure 1-1. AM1705 Functional Block Diagram 4 AM1705 ARM Microprocessor Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM1705 |
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