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AD8309-EVAL Fiches technique(PDF) 11 Page - Analog Devices |
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AD8309-EVAL Fiches technique(HTML) 11 Page - Analog Devices |
11 / 20 page REV. B AD8309 –11– The total dynamic range of the AD8309, defined as the ratio of the maximum permissible input to the noise floor, is thus 100 dB. Good accuracy is provided over a substantial part of this range. Input Matching Monolithic log amps present a nominal input impedance much higher than 50 Ω. For the AD8309, this can be modeled as 1 kΩ shunted by 2.5 pF, at frequencies up to 300 MHz. Thus, a simple input matching network can considerably improve the basic sensitivity , when driving from a low-impedance source, by increasing the voltage applied to the input. For a 50:1000 Ω transformation, the voltage gain is 13 dB, and the whole dy- namic range moves downward by this amount; that is, the inter- cept is shifted to –121 dBV (–108 dBm at the primary 50 Ω input). Note that while useful voltage gain is achieved in this way, it does not follow that the noise-figure is minimal at the optimum power match. Offset Control In a monolithic log amp, direct-coupling between the stages is invariably utilized for practical reasons. Now, a dc offset voltage in the early stages of the chain is indistinguishable from a “real” signal. If as high as 400 µV, it would be 20 dB larger than the smallest resolvable ac signal (40 µV), reducing the dynamic range by this amount. This problem is solved by using a global feedback path from the last stage to the first. The high-frequency components of the signal must be removed; this achieved in the AD8309 by an on-chip low-pass filter, providing sufficient sup- pression of HF feedback to allow accurate operation down to at least 5 MHz. Useful operation at lower frequencies remains possible, although a particular device having a large dc offset will exhibit a reduction in the low end region of the dynamic range. PRODUCT OVERVIEW The AD8309 is built on an advanced dielectrically-isolated complementary bipolar process using thin-film resistor technol- ogy for accurate scaling. It follows well-developed foundations proven over a period of some fifteen years, with constant refine- ment. The backbone of the AD8309 (Figure 25) comprises a chain of six main amplifier/limiter stages, each having a gain of 12.04 dB ( ×4) and small-signal –3 dB bandwidth of 850 MHz. The input interface at INHI and INLO (Pins 4 and 5) is fully differential. Thus it may be driven from either single-sided or balanced inputs, the latter being required at the very top end of the dynamic range, where the total differential drive may be as large as 4 V in amplitude. The first six stages, also used in developing the logarithmic RSSI output, are followed by a versatile programmable output, and thus programmable gain, final limiter section. Its open- collector outputs are also fully differential, at LMHI and LMLO (Pins 12 and 13). This output stage provides a gain of 18 dB when using equal valued load and bias setting resistors and the pin-to-pin output is used. The overall voltage gain is thus 100 dB. When using RLIM = RLOAD = 200 Ω, the additional current consumption in the limiter is approximately 2.8 mA, of which 2 mA goes to the load. The ratio depends on RLIM (for example, when 20 Ω, the efficiency is 90%), and the voltage at the pin LMDR is rather more than 400 mV, but the total load current is accurately (400 mV)/RLIM. The rise and fall times of the hard-limited (essentially square- wave) voltage at the outputs are typically 0.4 ns, when driven by a sine wave input having an amplitude of 100 mV or greater, and RLOAD = 50 Ω. The change in time-delay (“phase skew”) over the input range –83 dBV (100 mV in amplitude, or –70 dBm in 50 Ω) to –3 dBV (1 V or +10 dBm) is ±83 ps (±3° at 100 MHz). 12dB LIM DET 12dB DET DET 4 DET LADR ATTEN INHI INLO I-V BIAS CTRL TEN DETECTORS SPACED 12dB INTERCEPT TEMP COMP BAND-GAP REFERENCE ENBL GAIN BIAS LMHI LMLO LMDR VLOG FLTR SIX STAGES TOTAL GAIN 72dB TYP GAIN 18dB SLOPE BIAS 12dB Figure 25. Main Features of the AD8309 The six main cells and their associated full-wave detectors, having a transconductance (gm) form, handle the lower part of the dynamic range. Biasing for these cells is provided by two references, one of which determines their gain, the other being a band-gap cell which determines the logarithmic slope, and stabi- lizes it against supply and temperature variations. A special dc- offset-sensing cell (not shown in Figure 25) is placed at the end of this main section, and used to null any residual offset at the input, ensuring accurate response down to the noise floor. The first amplifier stage provides a short-circuited voltage-noise spectral-density of 1.07 nV/ √Hz. The last detector stage includes a modification to temperature- stabilize the log-intercept, which is accurately positioned so as to make optimal use of the full output voltage range. Four further “top end” detectors are placed at 12.04 dB taps along a passive attenuator, to handle the upper part of the range. The differen- tial current-mode outputs of all ten detectors stages are summed with equal weightings and converted to a single-sided voltage by the output stage, generating the logarithmic (or RSSI) output at VLOG (Pin 16), nominally scaled 20 mV/dB (that is, 400 mV per decade). The junction between the lower and upper regions is seamless, and the logarithmic law-conformance is typically well within ±0.4 dB from –83 dBV to +7 dBV (–70 dBm to +10 dBm). The full-scale rise time of the RSSI output stage, which operates as a two-pole low-pass filter with a corner frequency of 3.5 MHz, is about 200 ns. A capacitor connected between FLTR (Pin 10) and VLOG can be used to lower the corner frequency (see be- low). The output has a minimum level of about 0.34 V (corre- sponding to a noise power of –78 dBm, or 17 dB above the nominal intercept of –95 dBm). This rather high baseline level ensures that the pulse response remains unimpaired at very low inputs. The maximum RSSI output depends on the supply voltage and the load. An output of 2.34 V, that is, 20 mV/dB × (12 + 105) dB, is guaranteed when using a supply voltage of 4.5 V or greater and a load resistance of 50 Ω or higher, for a differential input of 9 dBV (a 4 V sine amplitude, using balanced drives). When using a 3 V supply, the maximum differential input may still be as high as –3 dBV (1 V sine amplitude), and the corresponding RSSI output of 2.1 V, that is, 20 mV/dB × (0 + 105) dB is also guaranteed. |
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Description similaire - AD8309-EVAL |
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