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AD5290YRMZ100-R7 Fiches technique(PDF) 7 Page - Analog Devices

No de pièce AD5290YRMZ100-R7
Description  Compact 30 V / 15,-15 V 256-Position Digital Potentiometer
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5290YRMZ100-R7 Fiches technique(HTML) 7 Page - Analog Devices

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Data Sheet
AD5290
Rev. C | Page 7 of 20
INTERFACE TIMING CHARACTERISTICS
Table 3.
Parameter 1, 2
Symbol
Conditions
Min
Typ
Max
Unit
Clock Frequency
fCLK
4
MHz
Input Clock Pulse Width
tCH, tCL
Clock level high or low
120
ns
Data Setup Time
tDS
30
ns
Data Hold Time
tDH
20
ns
CLK to SDO Propagation Delay3
tPD
RPull-up = 2.2 kΩ, CL < 20 pF
10
100
ns
CS Setup Time
tCSS
120
ns
CS High Pulse Width
tCSW
150
ns
CLK Fall to CS Fall Hold Time
tCSH0
10
ns
CLK Rise to CS Rise Hold Time
tCSH
120
ns
CS Rise to Clock Rise Setup
tCS1
120
ns
1
See Figure 3 for the location of the measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V. Switching characteristics are measured using VDD = +15 V and VSS = −15 V.
2
Guaranteed by design and not subject to production test.
3
Propagation delay depends on the value of VDD, RPull-up, and CL.


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