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HCPL-0723-500E Fiches technique(PDF) 8 Page - AVAGO TECHNOLOGIES LIMITED |
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HCPL-0723-500E Fiches technique(HTML) 8 Page - AVAGO TECHNOLOGIES LIMITED |
8 / 12 page 8 Switching Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA = +25°C,VDD1 =VDD2 = +5V. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time to Logic tPHL 16 22 ns CL = 15 pF CMOS Signal Levels; Figure 5 Low Output[3] Propagation Delay Time to Logic tPLH 16 22 ns CL = 15 pF CMOS Signal Levels; Figure 5 High Output[3] Pulse Width PW 20 ns CL = 15 pF CMOS Signal Levels Maximum Data Rate 50 MBd CL = 15 pF CMOS Signal Levels Pulse Width Distortion[4] |tPHL - tPLH| |PWD| 1 2 ns CL = 15 pF CMOS Signal Levels; Figure 6 Propagation Delay Skew[5] tPSK 16 ns CL = 15 pF CMOS Signal Levels Output Rise Time (10% – 90%) tR 8 ns CL = 15 pF CMOS Signal Levels Output Fall Time (90% - 10%) tF 6 ns CL = 15 pF CMOS Signal Levels Common Mode Transient Immunity |CMH| 10 15 kV/µs VCM = 1000V,TA = 25°C, at Logic High Output[6] VI =VDD1,VO > 0.8VDD2 Common Mode Transient Immunity |CML| 10 15 kV/µs VCM = 1000V,TA = 25°C, at Logic Low Output[6] VI = 0V,VO < 0.8V |
Numéro de pièce similaire - HCPL-0723-500E |
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Description similaire - HCPL-0723-500E |
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