Si3400/Si3401

Rev. 0.9

7

VDD accuracy @ 0.8 mA

36 V < VPORT < 57 V

4.5

—

5.5

V

Softstart charging current

—

12

—

µA

Thermal Shutdown

Junction temperature

—

160

—

ºC

Thermal Shutdown Hysteresis

—

—

25

ºC

Table 5. Total Power Dissipation

Description

Condition

Min

Typ

Max

Units

Power Dissipation

—

1.2

—

W

Power Dissipation*

bridges bypassed

—0.7

—

W

*Note: Silicon Laboratories recommends the on-chip diode bridges be bypassed when output power requirements are >10 W

(Si3401) or in thermally-constrained applications. For more information, see “AN313: Using the Si3400 and Si3401 in

High Power Applications”.

Table 6. Package Thermal Characteristics

Parameter

Symbol

Test Condition

Typ

Units

Thermal resistance

(junction to ambient)

Still air; assumes a minimum of

nine thermal vias are connected

the package “pad” node

(VNEG).

44

°C/W

Table 4. Electrical Characteristics (Continued)

Parameter

Description

Min

Typ

Max

Unit

Notes:

1. Transient surge defined in IEC60060 as a 1000 V impulse of either polarity applied to CT1–CT2 or SP1–SP2. The

shape of the impulse shall have a 300 ns full rise time and a 50 µs half fall time with 201

Ω source impedance.

2. The classification currents are guaranteed only when recommended RCLASS resistors are used, as specified in

Table 10.

3. IPORT includes full operating current of switching regulator controller.

4. The PD interface includes dual-level input current limit. At turn-on, before the HSO load capacitor is charged, the

current limit is set at the inrush level. After the capacitor has been charged within ~1.25 V of VNEG, the operating

current limit is engaged. This higher current limit remains active until the UVLO lower limit has been tripped or until the

hotswap switch is sufficiently current-limited to cause a foldback of the HSO voltage.

5. See “AN296: Using the Si3400/01 PoE PD Controller in Isolated and Non-Isolated Designs” for more information.

6. Applies to non-isolated applications only (VOUT on schematic in Figure 1).