ML4819

REV. 1.0 10/10/2000

5

FUNCTIONAL DESCRIPTION

OSCILLATOR

voltage reaches the upper threshold, the comparator

changes state and the capacitor discharges to the lower

threshold through Q1. While the capacitor is discharging,

the clock provides a high pulse.

The oscillator period can be described by the following

relationship:

where:

t=

C(Ramp Valley to Peak)

I

RAMP

SET

and:

t

C(Ramp Valley to Peak)

8.4mA - I

DEADTIME

SET

=

The maximum duty cycle of the PWM section can be

is above the threshold at pin 7, the PWM output is held

off and the PWM flip-flop is set:

D

D

(V

- 0.9)

3.4

LIMIT

OSC

PIN7

≅

×

where:

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

UNDER-VOLTAGE LOCKOUT

Start-Up Threshold

15

16

17

V

Shut-Down Threshold

9

10

11

V

4.4

V

SUPPLY

Supply Current

0.6

1.2

mA

35

mA

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

Note 3: PWM comparator bias currents are subtracted from this reading.

Figure 1. Oscillator Block Diagram

CLOCK

DUTY CYCLE

20

10

5V

+5V

TO PWM

LATCH B

TO PWM

LATCHES

8.4mA

Q1

CLOCK

RAMP PEAK

RAMP VALLEY

7

+

–

+

–