Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

AD7841BSZ Fiches technique(PDF) 8 Page - Analog Devices

No de pièce AD7841BSZ
Description  Octal 14-Bit, Parallel Input, Voltage-Output DAC
Download  13 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD7841BSZ Fiches technique(HTML) 8 Page - Analog Devices

Back Button AD7841BSZ Datasheet HTML 4Page - Analog Devices AD7841BSZ Datasheet HTML 5Page - Analog Devices AD7841BSZ Datasheet HTML 6Page - Analog Devices AD7841BSZ Datasheet HTML 7Page - Analog Devices AD7841BSZ Datasheet HTML 8Page - Analog Devices AD7841BSZ Datasheet HTML 9Page - Analog Devices AD7841BSZ Datasheet HTML 10Page - Analog Devices AD7841BSZ Datasheet HTML 11Page - Analog Devices AD7841BSZ Datasheet HTML 12Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 13 page
background image
AD7841
–8–
Unipolar Configuration
Figure 2 shows the AD7841 in the unipolar binary circuit
configuration. The VREF(+) input of the DAC is driven by the
AD586, a 5 V reference. VREF(–) is tied to ground. Table II
gives the code table for unipolar operation of the AD7841.
Other suitable references include the REF02, a precision 5 V
reference, and the REF195, a low dropout, micropower preci-
sion 5 V reference.
AD7841*
VDD
VCC
VREF(+)
VOUT
DUTGND
GND
VSS
VREF(–)
SIGNAL
GND
–15V
VOUT
(0 TO +10V)
+5V
+15V
AD586
R1
10k
2
6
5
4
8
C1
1 F
SIGNAL
GND
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 2. Unipolar 10 V Operation
Offset and gain may be adjusted in Figure 2 as follows: To
adjust offset, disconnect the VREF(–) input from 0 V, load the
DAC with all 0s and adjust the VREF(–) voltage until VOUT = 0 V.
For gain adjustment, the AD7841 should be loaded with all 1s
and R1 adjusted until VOUT = 2 VREF(+) – 1 LSB = 10 V(16383/
16384) = 9.99939 V.
Many circuits will not require these offset and gain adjustments.
In these circuits R1 can be omitted. Pin 5 of the AD586 may be
left open circuit and Pin 2 (VREF(–)) of the AD7841 tied to 0 V.
Table II. Code Table for Unipolar Operation
Binary Number in DAC Register
Analog Output
MSB
LSB
(VOUT)
11
1111
1111
1111
2 VREF (16383/16384) V
10
0000
0000
0000
2 VREF (8192/16384) V
01
1111
1111
1111
2 VREF (8191/16384) V
00
0000
0000
0001
2 VREF (1/16384) V
00
0000
0000
0000
0 V
NOTES
V= VREF(+); VREF(–) = 0 V for unipolar operation.
For VREF(+) = 5 V, 1 LSB = 10 V/2
14 = 10 V/16384 = 610
µV.
Bipolar Configuration
Figure 3 shows the AD7841 set up for
± 10 V operation. The
AD588 provides precision
±5 V tracking outputs that are fed to
the VREF(+) and VREF(–) inputs of the AD7841. The code table
for bipolar operation of the AD7841 is shown in Table III.
In Figure 3, full-scale and bipolar zero adjustments are provided
by varying the gain and balance on the AD588. R2 varies the
gain on the AD588 while R3 adjusts the offset of both the +5 V
and –5 V outputs together with respect to ground.
For bipolar-zero adjustment, the DAC is loaded with
1000... 0000 and R3 is adjusted until VOUT = 0 V. Full scale
is adjusted by loading the DAC with all 1s and adjusting R2
until VOUT = 10(8191/8192) V = 9.99878 V.
When bipolar-zero and full-scale adjustment are not needed, R2
and R3 can be omitted. Pin 12 on the AD588 should be con-
nected to Pin 11 and Pin 5 should be left floating.
AD7841*
VDD
VCC
VREF(+)
VOUT
DUTGND
GND
VSS
VREF(–)
SIGNAL
GND
–15V
VOUT
(–10V TO +10V)
+5V
+15V
*ADDITIONAL PINS OMITTED FOR CLARITY
R1
39k
C1
1 F
R2
100k
R3
100k
AD588
46
2
3
1
14
15
16
7
9
5
10
11
12
8 13
Figure 3. Bipolar
±10 V Operation
Table III. Code Table for Bipolar Operation
Binary Number in DAC
Register
Analog Output
MSB
LSB
(VOUT)
11
1111 1111
1111
2[VREF(–) + VREF (16383/16384)] V
10
0000 0000
0001
2[VREF(–) + VREF (8193/16384)] V
10
0000 0000
0000
2[VREF(–) + VREF (8192/16384)] V
01
1111 1111
1111
2[VREF(–) + VREF (8191/16384)] V
00
0000 0000
0001
2[VREF(–) + VREF (1/16384)] V
00
0000 0000
0000
2[VREF(–)] V
NOTES
VREF = (VREF(+) – VREF(–)).
For VREF(+) = +5 V, and VREF(–) = –5 V, VREF = 10 V, 1 LSB = 2 VREF V/2
14 =
20 V/16384 = 1.22 mV.
CONTROLLED POWER-ON OF THE OUTPUT STAGE
A block diagram of the output stage of the AD7841 is shown in
Figure 4. It is capable of driving a load of 5 k
Ω in parallel with
50 pF. G1 to G6 are transmission gates used to control the
power on voltage present at VOUT. On power up G1 and G2 are
also used in conjunction with the
CLR input to set V
OUT to the
user defined voltage present at the DUTGND pin. When
CLR
is taken back high, the DAC outputs reflect the data in the
DAC registers.
G1
G2
G4
G3
G6
G5
DUTGND
VOUT
R
R = 60k
14k
DAC
Figure 4. Block Diagram of AD7841 Output Stage
REV. B


Numéro de pièce similaire - AD7841BSZ

FabricantNo de pièceFiches techniqueDescription
logo
Analog Devices
AD7841BSZ AD-AD7841BSZ Datasheet
442Kb / 13P
   Octal 14-Bit, Parallel Input, Voltage-Output DAC
REV. B
More results

Description similaire - AD7841BSZ

FabricantNo de pièceFiches techniqueDescription
logo
Analog Devices
AD7841 AD-AD7841_15 Datasheet
442Kb / 13P
   Octal 14-Bit, Parallel Input, Voltage-Output DAC
REV. B
AD7841 AD-AD7841 Datasheet
167Kb / 12P
   Octal 14-Bit, Parallel Input, Voltage-Output DAC
REV. 0
AD7841BSZ AD-AD7841BSZ Datasheet
442Kb / 13P
   Octal 14-Bit, Parallel Input, Voltage-Output DAC
REV. B
AD7839ASZ AD-AD7839ASZ Datasheet
157Kb / 12P
   Octal 13-Bit, Parallel Input, Voltage-Output DAC
REV. 0
AD7839 AD-AD7839 Datasheet
153Kb / 12P
   Octal 13-Bit, Parallel Input, Voltage-Output DAC
REV. 0
AD7839 AD-AD7839_15 Datasheet
157Kb / 12P
   Octal 13-Bit, Parallel Input, Voltage-Output DAC
REV. 0
logo
Maxim Integrated Produc...
MAX7841 MAXIM-MAX7841 Datasheet
326Kb / 14P
   Octal, 14-Bit Voltage-Output DAC with Parallel Interface
Rev 0; 7/03
MAX5264 MAXIM-MAX5264 Datasheet
451Kb / 16P
   Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE
Rev 0; 5/00
logo
Wolfson Microelectronic...
WM2619 WOLFSON-WM2619 Datasheet
124Kb / 9P
   12-bit Parallel Input Voltage Output DAC
logo
Cadeka Microcircuits LL...
SPT5400 CADEKA-SPT5400 Datasheet
156Kb / 8P
   13-BIT, OCTAL VOLTAGE-OUTPUT DAC WITH PARALLEL INTERFACE
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com