AD9524 datasheet(1/56 Pages) AD

No de pièce	AD9524

Description	Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs

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Jitter Cleaner and Clock Generator with

6 Differential or 13 LVCMOS Outputs

Data Sheet

AD9524

Rev. D

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Tel: 781.329.4700

Technical Support

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FEATURES

Output frequency: <1 MHz to 1 GHz

Start-up frequency accuracy: <±100 ppm (determined by

VCXO reference accuracy)

Zero delay operation

Input-to-output edge timing: <±150 ps

6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS

6 dedicated output dividers with jitter-free adjustable delay

Adjustable delay: 63 resolution steps of ½ period of VCO

output divider

Output-to-output skew: <±50 ps

Duty-cycle correction for odd divider settings

Automatic synchronization of all outputs on power-up

Absolute output jitter: <200 fs at 122.88 MHz

Integration range: 12 kHz to 20 MHz

Distribution phase noise floor: −160 dBc/Hz

Digital lock detect

Nonvolatile EEPROM stores configuration settings

SPI- and I²C-compatible serial control port

Dual PLL architecture

PLL1

Low bandwidth for reference input clock cleanup with

external VCXO

Phase detector rate of 300 kHz to 75 MHz

Redundant reference inputs

Auto and manual reference switchover modes

Revertive and nonrevertive switching

Loss of reference detection with holdover mode

Low noise LVCMOS output from VCXO used for RF/IF

synthesizers

PLL2

Phase detector rate of up to 250 MHz

Integrated low noise VCO

APPLICATIONS

LTE and multicarrier GSM base stations

Wireless and broadband infrastructure

Medical instrumentation

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC,

and other 10 Gbps protocols

Forward error correction (G.710)

High performance wireless transceivers

ATE and high performance instrumentation

FUNCTIONAL BLOCK DIAGRAM

PLL1

REFA,

REFA

OUT0,

OUT0

OUT1,

OUT1

OUT4,

OUT4

OUT5,

OUT5

OSC

REFB,

REFB

REF_TEST

SCLK/SCL

SDIO/SDA

SDO

ZD_IN, ZD_IN

CONTROL

INTERFACE

(SPI AND I2C)

EEPROM

PLL2

ZERO

DELAY

AD9524

6-CLOCK

DISTRIBUTION

Figure 1.

GENERAL DESCRIPTION

The AD9524 provides a low power, multi-output, clock

distribution function with low jitter performance, along with an

on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to

4.0 GHz.

The AD9524 is defined to support the clock requirements for

long term evolution (LTE) and multicarrier GSM base station

designs. It relies on an external VCXO to provide the reference

jitter cleanup to achieve the restrictive low phase noise require-

ments necessary for acceptable data converter SNR performance.

The input receivers, oscillator, and zero delay receiver provide

both single-ended and differential operation. When connected

to a recovered system reference clock and a VCXO, the device

generates six low noise outputs with a range of 1 MHz to 1 GHz,

and one dedicated buffered output from the input PLL (PLL1).

The frequency and phase of one clock output relative to another

clock output can be varied by means of a divider phase select

function that serves as a jitter-free coarse timing adjustment in

increments that are equal to one-half the period of the signal

coming out of the VCO.

An in-package EEPROM can be programmed through the serial

interface to store user defined register settings for power-up and

chip reset.

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