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BU99901GUZ-WE2 Fiches technique(PDF) 3 Page - Rohm |
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BU99901GUZ-WE2 Fiches technique(HTML) 3 Page - Rohm |
3 / 26 page Datasheet Datasheet 3/23 TSZ02201-0R2R0G100280-1-2 © 2012 ROHM Co., Ltd. All rights reserved. 4.SEP.2012 Rev.001 www.rohm.com TSZ22111・15・001 BU99901GUZ-W (32Kbit) SDA SCL D0 ACK STOP CONDITION START CONDITION tWR WRITE DATA(n) ●Sync Data Input / Output Timing ○Input read at the rise edge of SCL ○Data output in sync with the fall of SCL Figure 1-(a). Sync data input / output timing Figure 1-(d). WP timing at write execution Figure 1-(b). Start - stop bit timing ○At write execution, in the area from the D0 taken clock rise of the first DATA(1), to tWR, set WP=“LOW”. ○By setting WP “HIGH” in the area, write can be cancelled. When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again. Figure 1-(e). WP timing at write cancels Figure 1-(c). Write cycle timing SDA SDA tHD :STA tHD :DAT tSU :DAT tBUF tPD tDH tLOW tHIGH tR tF SCL (Input) (Output) SCL SDA WP tHD:WP tWR D1 D0 ACK ACK DATA(1) DATA(n) tSU :WP Stop condition SDA tSU:STA tSU:STO tHD:STA START BIT STOP BIT SCL tHIGH:WP WP SDA D1 D0 ACK ACK DATA(1) DATA(n) tWR SCL tWR |
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