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TPS40007DGQRG4 Fiches technique(PDF) 3 Page - Texas Instruments |
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TPS40007DGQRG4 Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 28 page TPS40007 TPS40009 SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005 3 www.ti.com ELECTRICAL CHARACTERISTICS temperature range, TA = −40_C to 85_C, VDD = 5.0 V, TA = TJ; all parameters measured at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VDD Input voltage range 2.25 5.5 V VHGATE High-side gate voltage VBOOT − VSW 6 V Shutdown current SS/SD = 0 V, Outputs off 0.25 0.45 IDD Quiescent current FB = 0.8 V 1.4 2.0 mA IDD Switching current No load at HDRV/LDRV 1.5 4.0 mA UVLO Minimum on-voltage 1.95 2.05 2.15 V Hysteresis 80 150 220 mV OSCILLATOR fOSC Oscillator frequency TPS40007 2.25 V ≤ VDD ≤ 5.00 V 250 300 350 kHz fOSC Oscillator frequency TPS40009 2.25 V ≤ VDD ≤ 5.00 V 500 600 700 kHz VRAMP Ramp voltage VPEAK − VVALLEY 0.80 0.93 1.07 V Ramp valley voltage 0.24 0.31 0.44 V PWM Maximum duty cycle(2) TPS40007 FB = 0 V, VDD = 3.3 V 87.0% 94.0% Maximum duty cycle(2) TPS40009 FB = 0 V, VDD = 3.3 V 83.0% 93.0% Minimum duty cycle 0% Minimum controllable pulse width(1)(3) 100 150 ns ERROR AMPLIFIER VFB FB input voltage Line, Temperature 0.690 0.700 0.711 V VFB FB input voltage TA = 25°C 0.693 0.700 0.707 V IFB FB input bias current 30 130 nA VOH High-level output voltage FB = 0 V, IOH = 1.0 mA 2.0 2.5 V VOL Low-level output voltage FB =VDD, IOL = 0.5 mA 0.08 0.15 V IOH Output source current COMP = 0.7 V, FB = GND 2 6 mA IOL Output sink current COMP = 0.7 V, FB = VDD 3 8 mA GBW Gain bandwidth(1) 5 10 MHz AOL Open loop gain 55 85 dB SHORT CIRCUIT CURRENT PROTECTION ISINK ILIM sink current VDD = 5 V 11 15 19 µA ISINK ILIM sink current VDD = 2.25 V 9.5 13.0 16.5 µA VOS Offset voltage SW vs ILIM(1) 2.25 V ≤ VDD ≤ 5.00 −20 0 20 mV VILIM Input voltage range 2 VDD V tON Minimum HDRV pulse time in overcurrent VDD = 3.3 V 220 330 ns SW leading edge blanking pulse in over- current detection(1) 100 ns tSS Soft-start capacitor cycles as fault timer(1) 6 (1) Ensured by design. Not production tested. (2) Derate the maximum duty cycle by 3% for VDD < 3 V (3) Operating at PWM on-times of less than 100 ns could lead to overlap between HDRV and LDRV pulses. |
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