Moteur de recherche de fiches techniques de composants électroniques |
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SI5330C-A00207-GM Fiches technique(PDF) 7 Page - Silicon Laboratories |
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SI5330C-A00207-GM Fiches technique(HTML) 7 Page - Silicon Laboratories |
7 / 20 page Si5330 Rev. 1.0 7 HSTL Output Voltage VOH VDDO = 1.4 to 1.6 V 0.5xVDDO +0.3 — — V VOL —— 0.5xVDDO –0.3 V Duty Cycle* DC 45 — 55 % *Note: Input clock has a 50% duty cycle. Table 5. OEB Input Specifications Parameter Symbol Test Condition Min Typ Max Unit Input Voltage Low VIL — — 0.3 x VDD V Input Voltage High VIH 0.7 x VDD —— V Input Resistance RIN 20 — — k Table 6. Output Control Pins (LOS) (VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Condition Min Typ Max Unit Output Voltage Low VOL ISINK =3mA 0 — 0.4 V Rise/Fall Time 20–80% tR/tF CL < 10 pf, pull up 1k — — 10 ns Table 7. Jitter Specifications (VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C) Parameter Symbol Test Condition Min Typ Max Unit Additive Phase Jitter (12kHz–20MHz) tRPHASE 0.7 V pk-pk differential input clock at 622.08 MHz with 70 ps rise/fall time — 0.150 — ps RMS Additive Phase Jitter (50kHz–80MHz) tRPHASEWB 0.7 V pk-pk differential input clock at 622.08 MHz with 70 ps rise/fall time — 0.225 — ps RMS Table 8. Thermal Characteristics Parameter Symbol Test Condition Value Unit Thermal Resistance Junction to Ambient JA Still Air 37 °C/W Thermal Resistance Junction to Case JC Still Air 25 °C/W Table 4. Input and Output Clock Characteristics (Continued) (VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Units |
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