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SI4123-D-GT Fiches technique(PDF) 6 Page - Silicon Laboratories |
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SI4123-D-GT Fiches technique(HTML) 6 Page - Silicon Laboratories |
6 / 36 page Si4133 6 Rev. 1.61 Figure 1. SCLK Timing Diagram Table 4. Serial Interface Timing (V DD = 2.7 to 3.6 V, TA = –40 to 85 °C) Parameter1 Symbol Test Condition Min Typ Max Unit SCLK Cycle Time tclk Figure 1 40 — — ns SCLK Rise Time tr Figure 1 — — 50 ns SCLK Fall Time t f Figure 1 — — 50 ns SCLK High Time th Figure 1 10 — — ns SCLK Low Time tl Figure 1 10 — — ns SDATA Setup Time to SCLK 2 t su Figure 2 5 — — ns SDATA Hold Time from SCLK 2 thold Figure 2 0 — — ns SEN to SCLKDelay Time2 ten1 Figure 2 10 — — ns SCLK to SENDelay Time2 t en2 Figure 2 12 — — ns SEN to SCLKDelay Time2 ten3 Figure 2 12 — — ns SEN Pulse Width tw Figure 2 10 — — ns Notes: 1. All timing is referenced to the 50% level of the waveforms unless otherwise noted. 2. Timing is not referenced to 50% level of the waveform. See Figure 2. SCLK 80% 20% 50% t r t f t l t clk t h |
Numéro de pièce similaire - SI4123-D-GT |
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Description similaire - SI4123-D-GT |
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