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Si5315-EVB Fiches technique(PDF) 1 Page - Silicon Laboratories |
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Si5315-EVB Fiches technique(HTML) 1 Page - Silicon Laboratories |
1 / 54 page Rev. 1.0 4/12 Copyright © 2012 by Silicon Laboratories Si5315 Si5315 S YNCHRONOUS E THE RNET /TELECOM J ITTER A TTENUATI N G C LOCK M ULTIPLIER Features Applications Description The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 supports SyncE EEC options 1 and 2 when paired with a timing card that implements the required wander filter. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to 644.53 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SyncE and T1/E1 rates. The Si5315 is based on Silicon Laboratories' third-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user programmable, providing jitter performance optimization at the application level. Functional Block Diagram Provides jitter attenuation and frequency translation between SONET/PDH and Ethernet Supports ITU-T G.8262 Synchronous Ethernet equipment slave clock (EEC option 1 and 2) requirements with optional Stratum 3 compliant timing card clock source Two clock inputs/two clock outputs Input frequency range: 8 kHz–644 MHz Output frequency range: 8 kHz–644 MHz Ultra low jitter: 0.23 ps RMS (1.875–20 MHz) 0.47 ps RMS (12 kHz–20 MHz) Simple pin control interface Selectable loop bandwidth for jitter attenuation: 60 to 8.4 kHz Automatic/Manual hitless switching and holdover during loss of inputs clock Programmable output clock signal format: LVPECL, LVDS, CML or CMOS 40 MHz crystal or XO reference Single supply: 1.8, 2.5, or 3.3 V On-chip voltage regulator with high PSRR Loss of lock and loss of signal alarms Small size: 6 x 6 mm, 36-QFN Wide temperature range: –40 to +85 ºC Synchronous Ethernet line cards SONET OC-3/12/48 line cards PON OLT/ONU Carrier Ethernet switches routers MSAN / DSLAM T1/E1/DS3/E3 line cards DSPLL ® Clock In 1 Clock In 2 Clock Out 1 Clock Out 2 Clock 2 Disable/PLL Bypass Output Signal Format[1:0] XTAL/Clock VDD (1.8, 2.5, or 3.3 V) GND Status/Control Loss of Lock Loss of Signal 2 Frequency Select[3:0] Frequency Table Select Manual/Auto Clock Selection Clock Switch/Clock Active Indicator Loss of Signal 1 Loop Bandwidth Select[1:0] XTAL/Clock Si5315 Ordering Information: See page 48. Pin Assignments 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 FRQTBL AUTOSEL RST LOS2 LOS1 GND VDD XA CS_CA BWSEL0 BWSEL1 FRQSEL1 FRQSEL2 FRQSEL3 GND Pad FRQSEL0 GND 9 18 19 28 XB GND |
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Description similaire - Si5315-EVB |
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