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TPS3422EGDRYT Fiches technique(PDF) 2 Page - Texas Instruments |
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TPS3422EGDRYT Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 19 page TPS3420 TPS3421 TPS3422 SBVS211A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PRODUCT DESCRIPTION TPS3420xzzza x is the push-button timer option. TPS3421xyzzza y is the different reset timeout pulse option. TPS3422xyzzza zzz is the package designator. a is the tape or reel quantity. DEVICE FAMILY OPTIONS DEVICE CHANNELS INPUT RESET BEHAVIOR (DEASSERTION) TPS3420 2 NMOS-based threshold Input (PBx) dependent TPS3421 2 External pull-up to VCC Fixed pulse TPS3422 1 Internal pull-up Fixed pulse ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VALUE UNIT VCC –0.3 to +7 V RST –0.3 to +7 V Voltage PB1, PB2 –0.3 to +7 V TS –0.3 to VCC + 0.3 V Current RST pin ±20 mA Operating junction, TJ –40 to +125 °C Temperature(2) Storage, Tstg –65 to +150 °C Human body model (HBM) 2 kV Electrostatic discharge (ESD) ratings Charge device model (CDM) 500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute maximum- rated conditions for extended periods may affect device reliability. (2) As a result of the low dissipated power in this device, it is assumed that TJ = TA. THERMAL INFORMATION TPS3420 TPS3421 TPS3422 THERMAL METRIC(1) UNITS DRY (µSON) 6 PINS θJA Junction-to-ambient thermal resistance 322.0 θJCtop Junction-to-case (top) thermal resistance 1185.2 θJB Junction-to-board thermal resistance 184.7 °C/W ψJT Junction-to-top characterization parameter 34.9 ψJB Junction-to-board characterization parameter 182.6 θJCbot Junction-to-case (bottom) thermal resistance 69.6 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS3420 TPS3421 TPS3422 |
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