TC58NYG1S3EBAI5 datasheet(5/65 Pages) TOSHIBA

No de pièce	TC58NYG1S3EBAI5

Description	MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 GBIT (256M 횞 8 BIT) CMOS NAND E2PROM

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Fabricant	TOSHIBA [Toshiba Semiconductor]

Site Internet	http://www.semicon.toshiba.co.jp/eng

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TC58NYG1S3EBAI5

2011-03-01C

5

AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

(Ta

= -40 to 85℃, VCC = 1.7 to 1.95V)

SYMBOL

PARAMETER

MIN

MAX

UNIT

tCLS

CLE Setup Time

12

⎯

ns

tCLH

CLE Hold Time

5

⎯

ns

tCS

CE Setup Time

20

⎯

ns

tCH

CE Hold Time

5

⎯

ns

tWP

Write Pulse Width

12

⎯

ns

tALS

ALE Setup Time

12

⎯

ns

tALH

ALE Hold Time

5

⎯

ns

tDS

Data Setup Time

12

⎯

ns

tDH

Data Hold Time

5

⎯

ns

tWC

Write Cycle Time

25

⎯

ns

tWH

WE High Hold Time

10

⎯

ns

tWW

WP High to WE Low

100

⎯

ns

tRR

Ready to RE Falling Edge

20

⎯

ns

tRW

Ready to WE Falling Edge

20

⎯

ns

tRP

Read Pulse Width

12

⎯

ns

tRC

Read Cycle Time

25

⎯

ns

tREA

RE Access Time

⎯

20

ns

tCEA

CE Access Time

⎯

25

ns

tCLR

CLE Low to RE Low

10

⎯

ns

tAR

ALE Low to RE Low

10

⎯

ns

tRHOH

RE High to Output Hold Time

22

⎯

ns

tRLOH

RE Low to Output Hold Time

5

⎯

ns

tRHZ

RE High to Output High Impedance

⎯

60

ns

tCHZ

CE High to Output High Impedance

⎯

20

ns

tCSD

CE High to ALE or CLE Don’t Care

0

⎯

ns

tREH

RE High Hold Time

10

⎯

ns

tIR

Output-High-impedance-to- RE Falling Edge

0

⎯

ns

tRHW

RE High to WE Low

30

⎯

ns

tWHC

WE High to CE Low

30

⎯

ns

tWHR

WE High to RE Low

60

⎯

ns

tR

Memory Cell Array to Starting Address

⎯

25

µs

tDCBSYR1

Data Cache Busy in Read Cache (following 31h and

3Fh)

⎯

30

µs

tDCBSYR2

Data Cache Busy in Page Copy (following 3Ah)

⎯

35

µs

tWB

WE High to Busy

⎯

100

ns

tRST

Device Reset Time (Ready/Read/Program/Erase)

⎯

6/6/10/500

µs

*1: tCLS and tALS can not be shorter than tWP

*2: tCS should be longer than tWP + 8ns.

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