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74LVC1G74GD.125 Fiches technique(PDF) 11 Page - NXP Semiconductors |
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74LVC1G74GD.125 Fiches technique(HTML) 11 Page - NXP Semiconductors |
11 / 25 page 74LVC1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 12 — 2 April 2013 11 of 25 NXP Semiconductors 74LVC1G74 Single D-type flip-flop with set and reset; positive edge trigger 12. Waveforms Measurement points are given in Table 10. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to D hold times and the maximum frequency mnb141 th tsu th tPHL tPHL tPLH tPLH tsu 1/fmax tW VM VM VM VI GND VM VI GND CP input D input VOH VOL Q output VOH VOL Q output Table 10. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 V CC 0.5 V CC 2.3 V to 2.7 V 0.5 V CC 0.5 V CC 2.7V 1.5V 1.5V 3.0V to 3.6V 1.5V 1.5V 4.5 V to 5.5 V 0.5 V CC 0.5 V CC |
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