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FM31278 Fiches technique(PDF) 7 Page - Cypress Semiconductor

No de pièce FM31278
Description  5V Integrated Processor Companion with Memory
Download  26 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM31278 Fiches technique(HTML) 7 Page - Cypress Semiconductor

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FM31278/276 – 5V I2C Companion
Document Number: 001-86393 Rev. *B
Page 7 of 26
timekeeping registers. Updates to the timekeeping
core occur continuously except when locked.
Backup Power
The real-time clock/calendar is intended to be
permanently powered. When the primary system
power fails, the voltage on the VDD pin will drop.
When VDD is less 2.5V the RTC (and event counters)
will switch to the backup power supply on VBAK. The
clock operates at extremely low current in order to
maximize battery or capacitor life. However, one of
the advantages of combining a clock function with
the F-RAM memory is that data is not lost regardless
of the backup power source.
The IBAK current varies with temperature and voltage
(see DC parametric table). The following graph
shows IBAK as a function of VBAK. These curves are
useful for calculating backup time when a capacitor
is used as the VBAK source.
Figure 7. IBAK vs. VBAK Voltage
The minimum VBAK voltage varies linearly with
temperature. The user can expect the minimum VBAK
voltage to be 1.23V at +85°C and 1.90V at -40°C.
The tested limit is 1.55V at +25°C. The minimum
VBAK voltage has been characterized at -40°C and
+85°C but is not 100% tested.
Figure 8. VBAK (min.) vs. Temperature
Trickle Charger
To facilitate capacitor backup, the VBAK pin can
optionally provide a trickle charge current. When the
VBC bit, register 0Bh bit 2, is set to „1‟, the VBAK pin
will source approximately 80 µA until VBAK reaches
3.75V. In 5V systems, this charges the capacitor to
VDD without an external diode and resistor charger
and also prevents the user from exceeding the VBAK
maximum voltage specification. There is a Fast
Charge mode which is enabled by the FC bit (register
0Bh, bit 5). In this mode the trickle charger current is
set to approximately 1 mA, allowing a large backup
capacitor to charge more quickly.
In the case where no backup source is used, the VBAK
pin should be tied to VSS. VBAK should not be tied to
5V since the VBAK (max) specification will be
exceeded.
Be sure to turn off the trickle charger
(VBC=0), otherwise charger current will be shunted
to ground from VDD.
Note: systems using lithium batteries should clear
the VBC bit to 0 to prevent battery charging. The
VBAK circuitry includes an internal 1 K
series
resistor as a safety element. The trickle charger is UL
Recognized.
32.768 kHz
crystal
Oscillator
Clock
Divider
Update
Logic
512 Hz
W
R
Seconds
7 bits
Minutes
7 bits
Hours
6 bits
Date
6 bits
Months
5 bits
Years
8 bits
CF
Days
3 bits
User Interface Registers
1 Hz
/OSCEN
Figure 9. Real-Time Clock Core Block Diagram


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