Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

FM25CL64B-DG Fiches technique(PDF) 7 Page - Cypress Semiconductor

No de pièce FM25CL64B-DG
Description  64Kb Serial 3V F-RAM Memory
Download  17 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM25CL64B-DG Fiches technique(HTML) 7 Page - Cypress Semiconductor

Back Button FM25CL64B-DG Datasheet HTML 3Page - Cypress Semiconductor FM25CL64B-DG Datasheet HTML 4Page - Cypress Semiconductor FM25CL64B-DG Datasheet HTML 5Page - Cypress Semiconductor FM25CL64B-DG Datasheet HTML 6Page - Cypress Semiconductor FM25CL64B-DG Datasheet HTML 7Page - Cypress Semiconductor FM25CL64B-DG Datasheet HTML 8Page - Cypress Semiconductor FM25CL64B-DG Datasheet HTML 9Page - Cypress Semiconductor FM25CL64B-DG Datasheet HTML 10Page - Cypress Semiconductor FM25CL64B-DG Datasheet HTML 11Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 17 page
background image
FM25CL64B - 64Kb 3V SPI F-RAM
Document Number: 001-84477 Rev. *B
Page 7 of 17
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
The WPEN bit controls the effect of the hardware
/WP pin. When WPEN is low, the /WP pin is
ignored. When WPEN is high, the /WP pin controls
write access to the Status Register. Thus the Status
Register is write protected if WPEN=1 and /WP=0.
This scheme provides a write protection mechanism,
which can prevent software from writing the memory
under any circumstances. This occurs if the BP1 and
BP0 are set to 1, the WPEN bit is set to 1, and /WP is
set to 0. This occurs because the block protect bits
prevent writing memory and the /WP signal in
hardware prevents altering the block protect bits (if
WPEN is high). Therefore in this condition, hardware
must be involved in allowing a write operation. The
following table summarizes the write protection
conditions.
Table 4. Write Protection
WEL
WPEN
/WP
Protected Blocks
Unprotected Blocks
Status Register
0
X
X
Protected
Protected
Protected
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the F-RAM technology. Unlike SPI-bus
EEPROMs, the FM25CL64B can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Write Operation
All writes to the memory begin with a WREN op-
code with /CS being asserted and deasserted. The
next op-code is WRITE. The WRITE op-code is
followed by a two-byte address value. The upper 3-
bits of the address are ignored. In total, the 13-bits
specify the address of the first data byte of the write
operation. This is the starting address of the first data
byte of the write operation. Subsequent bytes are data
bytes, which are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks and keeps /CS low. If the
last address of 1FFFh is reached, the counter will roll
over to 0000h. Data is written MSB first. The rising
edge of /CS terminates a WRITE operation. A write
operation is shown in Figure 9.
EEPROMs use page buffers to increase their write
throughput. This compensates for the technology‟s
inherently slow write operations. F-RAM memories
do not have page buffers because each byte is written
to the F-RAM array immediately after it is clocked in
(after the 8
th clock). This allows any number of bytes
to be written without page buffer delays.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following the READ command is
a two-byte address value. The upper 3-bits of the
address are ignored. In total, the 13-bits specify the
address of the first byte of the read operation. This is
the starting address of the first byte of the read
operation. After the op-code and address are issued,
the device drives out the read data on the next 8
clocks.
The SI input is ignored during read data
bytes. Subsequent bytes are data bytes, which are
read out sequentially. Addresses are incremented
internally as long as the bus master continues to issue
clocks and /CS is low. If the last address of 1FFFh is
reached, the counter will roll over to 0000h. Data is
read MSB first. The rising edge of /CS terminates a
READ operation.
A read operation is shown in
Figure 10.
Hold
The /HOLD pin can be used to interrupt a serial
operation without aborting it. If the bus master pulls
the /HOLD pin low while SCK is low, the current
operation will pause. Taking the /HOLD pin high
while SCK is low will resume an operation. The
transitions of /HOLD must occur while SCK is low,
but the SCK pin can toggle during a hold state.


Numéro de pièce similaire - FM25CL64B-DG

FabricantNo de pièceFiches techniqueDescription
logo
Ramtron International C...
FM25CL64B-DG RAMTRON-FM25CL64B-DG Datasheet
307Kb / 14P
   64Kb Serial 3V F-RAM Memory
logo
Cypress Semiconductor
FM25CL64B-DG CYPRESS-FM25CL64B-DG Datasheet
509Kb / 14P
   64Kb Serial 3V F-RAM Memory
logo
Ramtron International C...
FM25CL64B-DGTR RAMTRON-FM25CL64B-DGTR Datasheet
307Kb / 14P
   64Kb Serial 3V F-RAM Memory
logo
Cypress Semiconductor
FM25CL64B-DGTR CYPRESS-FM25CL64B-DGTR Datasheet
509Kb / 14P
   64Kb Serial 3V F-RAM Memory
More results

Description similaire - FM25CL64B-DG

FabricantNo de pièceFiches techniqueDescription
logo
Cypress Semiconductor
FM24CL64B CYPRESS-FM24CL64B_13 Datasheet
342Kb / 13P
   64Kb Serial 3V F-RAM Memory
logo
Ramtron International C...
FM25CL64B RAMTRON-FM25CL64B Datasheet
307Kb / 14P
   64Kb Serial 3V F-RAM Memory
FM24CL64B RAMTRON-FM24CL64B Datasheet
225Kb / 12P
   64Kb Serial 3V F-RAM Memory
logo
Cypress Semiconductor
FM25CL64B CYPRESS-FM25CL64B Datasheet
509Kb / 14P
   64Kb Serial 3V F-RAM Memory
FM24CL64B CYPRESS-FM24CL64B Datasheet
354Kb / 13P
   64Kb Serial 3V F-RAM Memory
FM25CL64B-GA CYPRESS-FM25CL64B-GA Datasheet
425Kb / 15P
   Automotive Temp. 64Kb Serial 3V F-RAM Memory
FM24C64B CYPRESS-FM24C64B_13 Datasheet
352Kb / 15P
   64Kb Serial 5V F-RAM Memory
logo
Ramtron International C...
FM25640B RAMTRON-FM25640B Datasheet
213Kb / 13P
   64Kb Serial 5V F-RAM Memory
FM25640C RAMTRON-FM25640C Datasheet
321Kb / 13P
   64Kb Serial 5V F-RAM Memory
FM24C64B RAMTRON-FM24C64B Datasheet
293Kb / 12P
   64Kb Serial 5V F-RAM Memory
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com