CY14B512P

Document Number: 001-53872 Rev. *I

Page 29 of 35

Hardware STORE Cycle

Over the Operating Range

Parameter

Description

CY14B512P

Unit

Min

Max

Hardware STORE pulse width

15

–

ns

Switching Waveforms

Figure 32. Hardware STORE Cycle [28]

HSB (IN)

HSB (OUT)

RWI

HSB (IN)

HSB (OUT)

RWI

tHHHD

tSTORE

tPHSB

tDELAY

tLZHSB

tDELAY

tPHSB

HSB pin is driven HIGH to VCC only by Internal

100 K

resistor, HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven LOW.

Write Latch not set

Write Latch set

Note

28. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.