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CY14B512P Fiches technique(PDF) 1 Page - Cypress Semiconductor

No de pièce CY14B512P
Description  512-Kbit (64 K x 8) Serial (SPI) nvSRAM with Real Time Clock
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

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CY14B512P
512-Kbit (64 K × 8) Serial (SPI) nvSRAM
with Real Time Clock
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-53872 Rev. *I
Revised May 24, 2013
512-Kbit (64 K × 8) Serial (SPI) nvSRAM with Real Time Clock
Features
512-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 64 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by the user
using HSB pin (Hardware STORE) or SPI instruction
(Software STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by serial peripheral interface (SPI) instruction
(Software RECALL)
Automatic STORE on power-down with a small capacitor
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
Real time clock (RTC)
Full featured RTC
Watchdog timer
Clock alarm with programmable interrupts
Capacitor or battery backup for RTC
Backup current of 0.35 µA (typical)
High-speed SPI
40 MHz clock rate – SRAM memory access
25 MHz clock rate – RTC memory access
Supports SPI mode 0 (0,0) and mode 3 (1,1)
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4, 1/2, or entire array
Low power consumption
Single 3 V + 20%, –10% operation
Average active current of 10 mA at 40 MHz operation
Industry standard configurations
Industrial temperature
16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14B512P combines a 512-Kbit nvSRAM[1] with
a full-featured real time clock in a monolithic integrated circuit
with serial SPI interface. The memory is organized as 64 K words
of 8 bits each. The embedded nonvolatile elements incorporate
the QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile
elements
(STORE
operation)
takes
place
automatically at power-down. On power-up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
The STORE and RECALL operations can also be initiated by the
user through SPI instruction.
Instruction
register
Address
Decoder
Data I/O register
Status Register
Power Control
STORE/RECALL
Control
Instruction decode
Write protect
Control logic
QuantumTrap
STORE
RECALL
SI
SCK
VCC
V
CAP
SO
HSB
64 K X 8
SRAM Array
64 K X 8
RTC
X
X
INT
MUX
A0-A15
D0-D7
HOLD
CS
WP
out
in
Logic Block Diagram
Note
1. This device is referred to as nvSRAM throughout the document.


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