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74LVC14AD Fiches technique(PDF) 7 Page - NXP Semiconductors |
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74LVC14AD Fiches technique(HTML) 7 Page - NXP Semiconductors |
7 / 18 page 74LVC14A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 23 December 2011 7 of 18 NXP Semiconductors 74LVC14A Hex inverting Schmitt trigger with 5 V tolerant input Test data is given in Table 8. Definitions for test circuit: RL = Load resistance CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 7. Load circuitry for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aaf615 VCC VI VO DUT CL RT RL PULSE GENERATOR Table 8. Test data Supply voltage Input Load VI tr, tf CL RL 1.2 V VCC 2 ns 30 pF 1 k 1.65 V to 1.95 V VCC 2 ns 30 pF 1 k 2.3 V to 2.7 V VCC 2 ns 30 pF 500 2.7 V 2.7 V 2.5ns 50pF 500 3.0Vto 3.6V 2.7V 2.5ns 50pF 500 |
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