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ADF4118BRU Fiches technique(PDF) 7 Page - Analog Devices |
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ADF4118BRU Fiches technique(HTML) 7 Page - Analog Devices |
7 / 28 page ADF4116/ADF4117/ADF4118 Rev. D | Page 7 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADF4116/ ADF4117/ ADF4118 16 15 14 13 12 11 10 9 CP CPGND AGND AVDD RFINA RFINB FLO DVDD MUXOUT LE CE REFIN DGND CLK DATA VP TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 FLO Fast Lock Switch Output. This can be used to switch an external resistor to change the loop filter bandwidth and speed up locking the PLL. 2 CP Charge Pump Output. When enabled, this provides the ± ICP to the external loop filter, which in turn drives the external VCO. 3 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 AGND Analog Ground. This is the ground return path for the prescaler. 5 RFINB Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. See Figure 26. 6 RFINA Input to the RF Prescaler. This small signal input is ac-coupled from the VCO. 7 AVDD Analog Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must have the same value as DVDD. 8 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ. See Figure 25. The oscillator input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. 9 DGND Digital Ground. 10 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking the pin high powers up the device depending on the status of the power-down bit F2. 11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a high impedance CMOS input. 13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 14 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. 15 DVDD Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane (1 μF, 1 nF) should be placed as close as possible to this pin. For best performance, the 1 μF capacitor should be placed within 2 mm of the pin. The placing of the 1 nF capacitor is less critical, but should still be within 5 mm of the pin. DVDD must have the same value as AVDD. 16 VP Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, this supply can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V. |
Numéro de pièce similaire - ADF4118BRU |
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Description similaire - ADF4118BRU |
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