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AD7794CRUZ1 Fiches technique(PDF) 28 Page - Analog Devices |
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AD7794CRUZ1 Fiches technique(HTML) 28 Page - Analog Devices |
28 / 36 page AD7794/AD7795 Rev. D | Page 28 of 36 0 –20 –40 –60 –80 –100 0 3000 2500 2000 1500 1000 500 FREQUENCY (Hz) Figure 19. Filter Response at 242 Hz Update Rate (Chop Disabled) 0 –60 –50 –40 –30 –10 –20 0 10000 5000 6000 7000 8000 9000 4000 3000 2000 1000 FREQUENCY (Hz) Figure 20. Filter Response at 470 Hz Update Rate (Chop Disabled) DIGITAL INTERFACE As previously outlined in the On-Chip Registers section, the programmable functions of the AD7794/AD7795 are controlled using a set of on-chip registers. Data is written to these registers via the serial interface. Read access to the on-chip registers is also provided by this interface. All communications with the parts must start with a write to the communications register. After power-on or reset, each device expects a write to its communications register. The data written to this register determines whether the next operation is a read operation or a write operation, and determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the parts begins with a write operation to the communications register, followed by a write to the selected register. A read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register, followed by a read operation from the selected register. The serial interface of the AD7794/AD7795 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer data into the on-chip registers, while DOUT/RDY is used for accessing data from the on-chip registers. SCLK is the serial clock input for the devices, and all data transfers (either on DIN or DOUT/RDY) occur with respect to the SCLK signal. The DOUT/RDY pin also operates as a data ready signal; the line goes low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the data register to indicate when not to read from the device, to ensure that a data read is not attempted while the register is being updated. CS is used to select a device. It can be used to decode the AD7794/AD7795 in systems where several components are connected to the serial bus. Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7794/AD7795 with CS, which is being used to decode the parts. Figure 3 shows the timing for a read operation from the output shift register of the AD7794/AD7795, while Figure 4 shows the timing for a write operation to the input shift register. It is possible to read the same word from the data register several times, even though the DOUT/RDY line returns high after the first read operation. However, care must be taken to ensure that the read operations have been completed before the next output update occurs. In continuous read mode, the data register can be read only once. The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the AD7794/AD7795. The end of the conversion can be monitored using the RDY bit in the status register. This scheme is suitable for interfacing to micro- controllers. If CS is required as a decoding signal, it can be generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idle high between data transfers. The AD7794/AD7795 can be operated with CS being used as a frame synchronization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS, because CS normally occurs after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers are obeyed. The serial interface can be reset by writing a series of 1s on the DIN input. If a Logic 1 is written to the AD7794/AD7795 line for at least 32 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system. Reset returns the interface to the state in which it is expecting a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, the user should allow a period of 500 μs before addressing the serial interface. The AD7794/AD7795 can be configured to continuously convert or perform a single conversion (see Figure 21 through Figure 23). |
Numéro de pièce similaire - AD7794CRUZ1 |
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Description similaire - AD7794CRUZ1 |
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