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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD7730LBRU-REEL Fiches technique(PDF) 22 Page - Analog Devices |
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AD7730LBRU-REEL Fiches technique(HTML) 22 Page - Analog Devices |
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22 / 53 page  AD7730/AD7730L –22– CALIBRATION OPERATION SUMMARY The AD7730 contains a number of calibration options as outlined previously. Table XVII summarizes the calibration types, the operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor the hardware RDY pin using either interrupt-driven or polling routines. The second method is to do a software poll of the RDY bit in the Status Register. This can be achieved by setting up the part for continuous reads of the Status Register once a calibra- tion has been initiated. The RDY pin and RDY bit go high on initiating a calibration and return low at the end of the calibration routine. At this time, the MD2, MD1, MD0 bits of the Mode Register have returned to 0, 0, 0. The FAST and SKIP bits are treated as 0 for the calibration sequence so the full filter is always used for the calibration routines. See Calibration section for full detail. Table XVII. Calibration Operations MD2, MD1, Duration to RDY Duration to RDY Calibration Type MD0 Low (CHP = 1) Low (CHP = 0) Calibration Sequence Internal Zero-Scale 1, 0, 0 22 × 1/Output Rate 24 × 1/Output Rate Calibration on internal shorted input with PGA set for selected input range. The ac bit is ignored for this calibra- tion sequence. The sequence is performed with dc excitation. The Offset Calibration Register for the selected channel is updated at the end of this calibration sequence. For full self- calibration, this calibration should be preceded by an Internal Full-Scale calibration. For applications which require an Internal Zero-Scale and System Full-Scale calibration, this Internal Zero-Scale calibration should be performed first. Internal Full-Scale 1, 0, 1 44 × 1/Output Rate 48 × 1/Output Rate Calibration on internally-generated input full-scale with PGA set for selected input range. The ac bit is ignored for this calibration sequence. The sequence is performed with dc excitation. The Gain Calibration Register for the selected channel is updated at the end of this calibration sequence. It is recommended that internal full-scale calibrations are performed on the 80 mV range, regardless of the subsequent operating range, to optimize the post- calibration gain error. This calibration should be followed by either an Internal Zero-Scale or System Zero-Scale calibration. This zero-scale calibration should be performed at the operating input range. System Zero-Scale 1, 1, 0 22 × 1/Output Rate 24 × 1/Output Rate Calibration on externally applied input voltage with PGA set for selected input range. The input applied is assumed to be the zero scale of the system. If ac = 1, the system continues to use ac excitation for the duration of the calibration. For full system calibration, this System Zero- Scale calibration should be performed first. For applications which require a System Zero-Scale and Internal Full-Scale calibration, this calibration should be preceded by the Internal Full-Scale calibration. The Offset Calibration Register for the selected channel is updated at the end of this calibration sequence. System Full-Scale 1, 1, 1 22 × 1/Output Rate 24 × 1/Output Rate Calibration on externally-applied input voltage with PGA set for selected input range. The input applied is assumed to be the full-scale of the system. If ac = 1, the system continues to use ac excitation for the duration of the calibration. This calibration should be preceded by a System Zero-Scale or Internal Zero-Scale calibration. The Gain Calibration Register for the selected channel is updated at the end of this calibration sequence. REV. B |
Numéro de pièce similaire - AD7730LBRU-REEL |
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Description similaire - AD7730LBRU-REEL |
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