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AD7715AN-3 Fiches technique(PDF) 33 Page - Analog Devices |
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AD7715AN-3 Fiches technique(HTML) 33 Page - Analog Devices |
33 / 40 page AD7715 Rev. D | Page 33 of 40 AD7715 TO 8XC51 INTERFACE An interface circuit between the AD7715 and the 8XC51 microcontroller is shown in Figure 12. The diagram shows the minimum number of interface connections with CS on the AD7715 hardwired low. In the case of the 8XC51 interface, the minimum number of interconnects is just two. In this scheme, the DRDY bit of the communications register is monitored to determine when the data register is updated. The alternative scheme, which increases the number of interface lines to three, is to monitor the DRDY output line from the AD7715. The monitoring of the DRDY line can be done in two ways. First, DRDY can be connected to one of the 8XC51’s port bits (such as P1.0) which is configured as an input. This port bit is then polled to determine the status of DRDY. The second scheme is to use an interrupt driven system in which case, the DRDY output is connected to the INT1 input of the 8XC51. For interfaces that require control of the CS input on the AD7715, one of the port bits of the 8XC51 (such as P1.1), which is configured as an output, can be used to drive the CS input. The 8XC51 is configured in its Mode 0 serial interface mode. Its serial interface contains a single data line. As a result, the DOUT and DIN pins of the AD7715 should be connected together with a 10 kΩ pull-up resistor. The serial clock on the 8XC51 idles high between data transfers. The 8XC51 outputs the LSB first in a write operation while the AD7715 rearranged before being written to the output serial register. Similarly, the AD7715 outputs the MSB first during a read operation while the 8XC51 expects the LSB first. Therefore, the data which is read into the serial buffer needs to be rearranged before the correct data word from the AD7715 is available in the accumulator. AD7715 DOUT 8XC51 DIN SCLK P3.0 P3.1 10k Ω RESET DVDD DVDD CS Figure 12. AD7715 to 8XC51 Interface AD7715 TO ADSP-2103/ADSP-2105 INTERFACE Figure 13 shows an interface between the AD7715 and the ADSP-2103/ADSP-2105 DSP processor. In the interface shown, the DRDY bit of the communications register is monitored to determine when the data register is updated. The alternative scheme is to use an interrupt driven system, in which case the DRDY output is connected to the IRQ2 input of the ADSP-2103/ ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105 is set up for alternate framing mode. The RFS and TFS pins of the ADSP-2103/ADSP-2105 are configured as active low outputs, and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is also configured as an output. The CS for the AD7715 is active when either the RFS or TFS outputs from the ADSP- 2103/ADSP-2105 are active. The serial clock rate on the ADSP- 2103/ADSP-2105 should be limited to 3 MHz to ensure correct operation with the AD7715. DVDD AD7715 DOUT ADSP-2103/ ADSP-2105 DIN SCLK RFS DR DT TFS SCLK RESET CS Figure 13. AD7715 to ADSP-2103/ADSP-2105 Interface |
Numéro de pièce similaire - AD7715AN-3 |
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Description similaire - AD7715AN-3 |
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