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EVAL-AD7470CB2 Fiches technique(PDF) 12 Page - Analog Devices |
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EVAL-AD7470CB2 Fiches technique(HTML) 12 Page - Analog Devices |
12 / 20 page REV. B AD7470/AD7472 –12– PARALLEL INTERFACE The parallel interfaces of the AD7470 and AD7472 are 10 bits and 12 bits wide, respectively. The output data buffers are acti- vated when both CS and RD are logic low. At this point, the con- tents of the data register are placed onto the data bus. Figure 10 shows the timing diagram for the parallel port. Figure 11 shows the timing diagram for the parallel port when CS and RD are tied permanently low. In this setup, once BUSY line goes from high to low, the conversion process is completed. The data is available on the output bus slightly before the falling edge of BUSY. It is important to point out that data bus cannot change state while the ADC is doing a conversion as this would have a detri- mental effect on the conversion in progress. The data out lines will go three-state again when either the RD or the CS line goes high. Thus the CS can be tied low permanently, leaving the RD line to control conversion result access. Refer to VDRIVE section for output voltage levels. t2 tCONVERT t3 t4 t8 t5 t6 t7 t9 t10 BUSY CS RD DBx CONVST* * CONVST SHOULD GO HIGH WHEN THE CLK IS HIGH OR BEFORE THE FIRST CLK CYCLE. Figure 10. Parallel Port Timing t2 tCONVERT t9 CONVST* BUSY DBx DATA N DATA N + 1 * CONVST SHOULD GO HIGH WHEN THE CLK IS HIGH OR BEFORE THE FIRST CLK CYCLE. Figure 11. Parallel Port Timing with CS and RD Tied Low t2 t3 t4 t8 t6 t7 CLK IN CONVST BUSY CS RD DBX tWAKEUP t5 tCONVERT Figure 12. Wake-Up Timing Diagram (Burst Clock) |
Numéro de pièce similaire - EVAL-AD7470CB2 |
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