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EVAL-CONTROLBRD33 Fiches technique(PDF) 22 Page - Analog Devices |
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EVAL-CONTROLBRD33 Fiches technique(HTML) 22 Page - Analog Devices |
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22 / 32 page  AD7621 Rev. 0 | Page 22 of 32 PREVIOUS CONVERSION t13 t12 t3 BUSY DATA BUS CNVST, RD CS = 0 t4 t1 Figure 35. Slave Parallel Data Timing for Reading (Read During Convert) 8-Bit Interface (Master or Slave) The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in Figure 36, when BYTESWAP is low, the LSB byte is output on D[7:0] and the MSB is output on D[15:8]. When BYTESWAP is high, the LSB and MSB bytes are swapped, and the LSB is output on D[15:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16-bit data can be read in two bytes on either D[15:8] or D[7:0]. This interface can be used in both master and slave parallel reading modes. CS RD BYTESWAP PINS D[15:8] PINS D[7:0] HI-Z HI-Z HIGH BYTE LOW BYTE LOW BYTE HIGH BYTE HI-Z HI-Z t12 t12 t13 Figure 36. 8-Bit and 16-Bit Parallel Interface SERIAL INTERFACE The AD7621 is configured to use the serial interface when SER/PAR is held high. The AD7621 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock. MASTER SERIAL INTERFACE Internal Clock The AD7621 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7621 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted, if desired. Depending on the read during convert input, RDC/SDIN, the data can be read after each conversion or during the following conversion. Figure 37 and Figure 38 show detailed timing diagrams of these two modes. Usually, because the AD7621 is used with a fast throughput, the master read during conversion mode is the most recommended serial mode. In this mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions. In this mode, the SCLK period changes since the LSBs require more time to settle and the SCLK is derived from the SAR conversion cycle. In read after conversion mode, unlike other modes, the BUSY signal returns low after the 16 data bits are pulsed out and not at the end of the conversion phase resulting in a longer BUSY width. As a result, the maximum throughput cannot be achieved in this mode. |
Numéro de pièce similaire - EVAL-CONTROLBRD33 |
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Description similaire - EVAL-CONTROLBRD33 |
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