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AD5551BRZ-REEL7 Fiches technique(PDF) 14 Page - Analog Devices |
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AD5551BRZ-REEL7 Fiches technique(HTML) 14 Page - Analog Devices |
14 / 16 page AD5551/AD5552 Rev. A | Page 14 of 16 MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5551/AD5552 is via a serial bus that uses standard protocol compatible with DSP processors and microcontrollers. The communications channel requires a 3-wire interface consisting of a clock signal, a data signal and a synchronization signal. The AD5551/AD5552 require a 14-bit data word with data valid on the rising edge of SCLK. The DAC update may be done automatically when all the data is clocked in or it may be done under control of LDAC (AD5552 only). ADSP-21xx TO AD5551/AD5552 INTERFACE Figure 25 shows a serial interface between the AD5551/AD5552 and the ADSP-21xx. The ADSP-21xx should be set to operate in the SPORT (serial port) transmit alternate framing mode. The ADSP-21xx is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, 16-bit word length. The first 2 bits are don’t care as AD5551/AD5552 keeps the last 14 bits. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. Because of the edges-triggered difference, an inverter is required at the SCLKs between the DSP and the DAC. DIN SCLK DT SCLK AD5551/ AD5552* ADSP-21xx* *ADDITIONAL PINS OMITTED FOR CLARITY. **AD5552 ONLY. CS TFS LDAC** FO Figure 25. ADSP-21xx to AD5551/AD5552 Interface 68HC11 TO AD5551/AD5552 INTERFACE Figure 26 shows a serial interface between the AD5551/AD5552 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC, while the MOSI output drives the serial data line DIN. CS signal is driven from one of the port lines. The 68HC11 is configured for master mode; MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI output is valid on the rising edge of SCK. DIN SCLK MOSI SCK AD5551/ AD5552* 68HC11/ 68L11* *ADDITIONAL PINS OMITTED FOR CLARITY. **AD5552 ONLY. CS PC7 LDAC** PC6 Figure 26. 68HC11/68L11 to AD5551/AD5552 Interface MICROWIRE TO AD5551/AD5552 INTERFACE Figure 27 shows an interface between the AD5551/AD5552 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD5551/ AD5552 on the rising edge of the serial clock. No glue logic is required as the DAC clocks data into the input shift register on the rising edge. DIN SCLK SO SCLK AD5551/ AD5552* MICROWIRE* *ADDITIONAL PINS OMITTED FOR CLARITY. CS CS Figure 27. MICROWIRE to AD5551/AD5552 Interface 80C51/80L51 TO AD5551/AD5552 INTERFACE A serial interface between the AD5551/AD5552 and the 80C51/ 80L51 microcontroller is shown in Figure 28. TxD of the micro- controller drives the SCLK of the AD5551/AD5552, while RxD drives the serial data line of the DAC. P3.3 is a bit programmable pin on the serial port which is used to drive CS. DIN SCLK RxD TxD AD5551/ AD5552* 80C51/ 80L51* *ADDITIONAL PINS OMITTED FOR CLARITY. **AD5552 ONLY. CS P3.3 LDAC** P3.4 Figure 28. 80C51/80L51 to AD5551/AD5552 Interface The 80C51/80L51 provides the LSB first, while the AD5551/ AD5552 expect the MSB of the 14-bit word first. Take care to ensure that the transmit routine takes this into account. Usually it can be done through software by shifting out and accumu- lating the bits in the correct order before inputting to the DAC. Also, 80C51 outputs 2 byte words/16 bits data, thus the first two bits, after rearrangement, should be don’t care as they are dropped from the 14-bit word of the DAC. When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is valid on the falling edge of TxD, so the clock must be inverted as the DAC clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 transmits its data in 8-bit bytes with only eight falling clock edges occur- ring in the transmit cycle. As the DAC requires a 14-bit word, P3.3 (or any one of the other programmable bits) is the CS input signal to the DAC, so P3.3 should be brought low at the beginning of the 16-bit write cycle 2 × 8 bit words and held low until the 16-bit 2 × 8 cycle is completed. After that, P3.3 is brought high again and the new data loads to the DAC. Again, the first two bits, after rearranging, should be don’t care. LDAC on the AD5552 may also be controlled by the 80C51/80L51 serial port output by using another bit programmable pin, P3.4. |
Numéro de pièce similaire - AD5551BRZ-REEL7 |
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Description similaire - AD5551BRZ-REEL7 |
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