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AD5551BRZ-REEL7 Fiches technique(PDF) 11 Page - Analog Devices |
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AD5551BRZ-REEL7 Fiches technique(HTML) 11 Page - Analog Devices |
11 / 16 page AD5551/AD5552 Rev. A | Page 11 of 16 THEORY OF OPERATION The AD5551/AD5552 are single, 14-bit, serial input, voltage output DACs. They operate from a single supply ranging from 2.7 V to 5.5 V and consume typically 125 μA with a supply of 5 V. Data is written to these devices in a 14-bit word format, via a 3-or 4-wire serial interface. To ensure a known power-up state, these parts were designed with a power-on reset function. In unipolar mode, the output is reset to 0 V, while in bipolar mode, the AD5552 output is set to −VREF. Kelvin sense connections for the reference and analog ground are included on the AD5552. DIGITAL-TO-ANALOG SECTION The DAC architecture consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 22. The DAC architecture of the AD5551/AD5552 is segmented. The four MSBs of the 14-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either AGND or VREF. The remaining 10 bits of the data word drive switches S0 to S9 of a 10-bit voltage mode R-2R ladder network. 2R . . . . . S1 . . . . . 2R S9 2R E1 2R . . . . . E2 . . . . . 2R 2R S0 2R E15 R R VREF VOUT 10-BIT R-2R LADDER FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS Figure 22. DAC Architecture With this type of DAC configuration, the output impedance is independent of code, while the input impedance seen by the reference is heavily code dependent. The output voltage is dependent on the reference voltage as shown in the following equation: N REF OUT D V V 2 × = where: D is the decimal data word loaded to the DAC register. N is the resolution of the DAC. For a reference of 2.5 V, the equation simplifies to the following, 384 , 16 5 . 2 D V OUT × = This gives a VOUT of 1.25 V with midscale loaded, and a VOUT of 2.5 V with full-scale loaded to the DAC. The LSB size is VREF/16,384. SERIAL INTERFACE The AD5551/AD5552 are controlled by a versatile 3-wire serial interface, which operates at clock rates up to 25 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. The timing diagram can be seen in Figure 3. Input data is framed by the chip select input, CS. After a high-to-low transition on CS, data is shifted synchronously and latched into the input register on the rising edge of the serial clock, SCLK. Data is loaded MSB first in 14-bit words. After 14 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the DAC. Data can only be loaded to the part while CS is low. The AD5552 has an LDAC function that allows the DAC latch to be updated asynchronously by bringing LDAC low after CS goes high. LDAC should be maintained high while data is written to the shift register. Alternatively, LDAC may be tied permanently low to update the DAC synchronously. With LDAC tied permanently low, the rising edge of CS loads the data to the DAC. UNIPOLAR OUTPUT OPERATION These DACs are capable of driving unbuffered loads of 60 kΩ. Unbuffered operation results in low-supply current, typically 300 μA, and a low-offset error. The AD5551 provides a unipolar output swing ranging from 0 V to VREF. The AD5552 can be con- figured to output both unipolar and bipolar voltages. Figure 23 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table 6. VOUT VREFF* DGND AGND VDD DIN SCLK CS AD5551/ AD5552 AD820/ OP196 VREFS* 0.1µF 0.1µF 10µF UNIPOLAR OUTPUT EXTERNAL OP AMP 2.5V 5V LDAC* *AD5552 ONLY. SERIAL INTERFACE Figure 23. Unipolar Output Table 6. Unipolar Code Table DAC Latch Contents MSB LSB Analog Output 11 1111 1111 1111 VREF × (16,383/16,384) 10 0000 0000 0000 VREF × (8192/16,384) = ½ VREF 00 0000 0000 0001 VREF × (1/16,384) 00 0000 0000 0000 0 V |
Numéro de pièce similaire - AD5551BRZ-REEL7 |
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Description similaire - AD5551BRZ-REEL7 |
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