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TC1320EOA Fiches technique(PDF) 3 Page - Microchip Technology

No de pièce TC1320EOA
Description  8-Bit Digital-to-Analog Converter with Two-Wire Interface
Download  16 Pages
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Fabricant  MICROCHIP [Microchip Technology]
Site Internet  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

TC1320EOA Fiches technique(HTML) 3 Page - Microchip Technology

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 2002-2012 Microchip Technology Inc.
DS21386C-page 3
TC1320
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings*
Supply Voltage (VDD) .............................................+6V
Voltage on any Pin .. (GND – 0.3V) to (VDD + 0.3V)
Current on any Pin ............................................ ±50mA
Package Thermal Resistance (
JA)............ 330°C C/W
Operating Temperature (TA)........................ See Below
Storage Temperature (TSTG) .............. -65°C to +150°C
*Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device
at these or any other conditions above those indicated in the
operation sections of the specifications is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
TC1320 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: VDD = 2.7V to 5.5V, -40°C  TA  +85°C, VREF = 1.2V unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
Power Supply
VDD
Supply Voltage
2.7
350
500
A
IDD
Operating Current
0.35
0.5
mA
VDD = 5.5V, VREF = 1.2V
Serial Port Inactive (Note 1)
IDD-STANDBY Standby Supply Current
0.1
1
AV
DD = 3.3V
Serial Port Inactive (Note 1)
Static Performance - Analog Section
Resolution
8
Bits
INL
Integral Non-Linearity at FS, TA = +25°C
±2
LSB
(Note 2)
FSE
Full Scale Error
±3
%FS
DNL
Differential Non-Linearity, TA = +25°C
±0.8
LSB
All Codes (Note 2)
VOS
Offset Error at VOUT
—±0.3
±8
mV
(Note 2)
TCVOS
Offset Error Tempco at VOUT
—10
v/°C
PSRR
Power Supply Rejection Ratio
80
dB
VDD at DC
VREF
Voltage Reference Range
0
VDD – 1.2
V
IREF
Reference Input Leakage Current
±1.0
A
VSW
Voltage Swing
0
VREF
VVREF  (VDD – 1.2V)
ROUT
Output Resistance @ VOUT
—5
ROUT ()
IOUT
Output Current (Source or Sink)
2
mA
ISC
Output Short-Circuit Current
VDD = 5.5V
30
20
50
50
mA
mA
Source
Sink
Dynamic Performance
SR
Voltage Output Slew Rate
0.8
V/
s
tSETTLE
Output Voltage Full Scale Settling Time
10
sec
tWU
Wake-up Time
20
s
Digital Feed Through and Crosstalk
5
nV-s
SDA = VDD, SCL = 100kHz
Serial Port Interface
VIH
Logic Input High
2.4
VDD
V
VIL
Logic Input Low
0.6
VOL
SDA Output Low
0.4
0.6
V
V
IOL = 3mA (Sinking Current)
IOL = 6mA
CIN
Input Capacitance SDA, SCL
5
0.4
pF
ILEAK
I/O Leakage
±1.0
A
Note
1: SDA and SCL must be connected to VDD or GND.
2: Measured at VOUT 50mV referred to GND to avoid output buffer clipping.


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