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SST38VF6401B Fiches technique(PDF) 8 Page - Microchip Technology |
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SST38VF6401B Fiches technique(HTML) 8 Page - Microchip Technology |
8 / 58 page SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B DS25002B-page 8 Preliminary 2013 Microchip Technology Inc. 4.0 DEVICE OPERATION The memory operations functions of these devices are initiated using commands written to the device using standard microprocessor Write sequences. A com- mand is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST38VF6401B/6402B/6403B/6404B also have the Auto Low Power mode which puts the device in a near- standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 6 mA to typically 5 µA. The device requires no access time to exit the Auto Low Power mode after any address transition or control signal tran- sition used to initiate another Read cycle. The device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address tran- sition or CE# is driven high. 4.1 Read The Read operation of the SST38VF6401B/6402B/ 6403B/6404B is controlled by CE# and OE#, both of which have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to Figure 6-1, the Read cycle timing dia- gram, for further details. 4.2 Page Read The Page Read operation utilizes an asynchronous method that enables the system to read data from the SST38VF6401B/6402B/6403B/6404B at a faster rate. This operation allows users to read an eight-word page of data at an average speed of 33 ns per word. In Page Read, the initial word read from the page requires TACC to be valid, while the remaining seven words in the page require only TPACC. All eight words in the page have the same address bits, A21-A3, which are used to select the page. Address bits A2-A0 are tog- gled, in any order, to read the words within the page. The Page Read operation of the SST38VF6401B/ 6402B/6403B/6404B is controlled by CE# and OE#. Both CE# and OE# must be low for the system to obtain data from the output pins. CE# controls device selec- tion. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to Figure 6-2, the Page Read cycle timing diagram, for further details. 4.3 Word-Program Operation The SST38VF6401B/6402B/6403B/6404B can be pro- grammed on a word-by-word basis. Before program- ming, the block where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, which- ever occurs first. The Program operation, once initi- ated, will be completed within 7 µs. See Figures 6-3 and 6-4 for WE# and CE# controlled Program opera- tion timing diagrams and Figure 6-19 for flowcharts. During the Program operation, the only valid reads are Data# Polling, Toggle Bits, and RY/BY#. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low. When programming more than a few words, Microchip recommends Write-Buffer Programming. 4.4 Write-Buffer Programming The SST38VF6401B/6402B/6403B/6404B offer Write- Buffer Programming, a feature that enables faster effective word programming. To use this feature, write up to 16 words with the Write-to-Buffer command, then use the Program Buffer-to-Flash command to program the Write-Buffer to memory. The Write-to-Buffer command consists of between 5 and 20 write cycles. The total number of write cycles in the Write-to-Buffer command sequence is equal to the number of words to be written to the buffer plus four. The first three cycles in the command sequence tell the device that a Write-to-Buffer operation will begin. The fourth cycle tells the device the number of words to be written into the buffer and the block address of these words. Specifically, the write cycle consists of a block address and a data value called the Word Count (WC), which is the number of words to be written to the buffer minus one. If the WC is greater than 15, the maximum buffer size minus 1, then the operation aborts. For the fifth cycle, and all subsequent cycles of the Write-to-Buffer command, the command sequence consists of the addresses and data of the words to be written into the buffer. All of these cycles must have the same A21 - A4 address, otherwise the operation aborts. The number of Write cycles required is equal to the number of words to be written into the Write-Buffer, which is equal to WC plus one. The correct number of |
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