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AD420AN-32 Fiches technique(PDF) 11 Page - Analog Devices |
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AD420AN-32 Fiches technique(HTML) 11 Page - Analog Devices |
11 / 16 page AD420 Rev. H | Page 11 of 16 THREE-WIRE INTERFACE Figure 9 shows the AD420 connected in the 3-wire interface mode. The AD420 data input block contains a serial input shift register and a parallel latch. The contents of the shift register are controlled by the DATA IN signal and the rising edges of the CLOCK. Upon request of the LATCH pin the DAC and internal latch are updated from the shift register parallel outputs. The CLOCK should remain inactive while the DAC is updated. Refer to the timing requirements for 3-wire interface. FAULT DETECT FAULT DETECT DATA IN CLOCK GND LATCH DATA IN CLOCK LATCH VCC RLOAD VCC IOUT DATA OUT AD420 DAC1 FAULT DETECT DATA IN CLOCK GND LATCH VCC VLL RLOAD VCC IOUT DATA OUT AD420 DAC2 10kΩ Figure 9. Three-Wire Interface Using Multiple DACs with Joint Fault Detect USING MULTIPLE DACS WITH FAULT DETECT The 3-wire interface mode can utilize the serial DATA OUT for easy interface to multiple DACs. To program the two AD420s in Figure 9, 32 data bits are required. The first 16 bits are clocked into the input shift register of DAC1. The next 16 bits transmitted pass the first 16 bits from the DATA OUT pin of DAC1 to the input register of DAC2. The input shift registers of the two DACs operate as a single 32-bit shift register, with the leading 16 bits representing information for DAC2 and the trailing 16 bits serving for DAC1. Each DAC is then updated upon request of the LATCH pin. The daisy-chain can be extended to as many DACs as required. ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS The AD420 connected in asynchronous interface mode with optocouplers is shown in Figure 10. Asynchronous operation minimizes the number of control signals required for isolation of the digital system from the control loop. The resistor connected between the LATCH pin and VCC is required to activate this mode. For operation with VCC below 18 V use a 50 kΩ pull-up resistor; from 18 V to 32 V, use 100 kΩ. Asynchronous mode requires that the clock run at 16 times the data bit rate, therefore, to operate at the maximum input data rate of 150 kBPS, an input clock of 2.4 MHz is required. The actual data rate achieved may be limited by the type of optocouplers chosen. The number of control signals can be further reduced by creating the appropriate clock signal on the current loop side of the isolation barrier. If optocouplers with relatively slow rise and fall times are used, Schmitt triggers may be required on the digital inputs to prevent erroneous data being presented to the DAC. 8 2 7 23 9 11 VCC +24V +5V VLL LATCH 100kΩ AD420 CLOCK DATA IN ISOLATION GALVANIC BARRIER CLOCK DATA GND Figure 10. Asynchronous Interface Using Optocouplers |
Numéro de pièce similaire - AD420AN-32 |
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Description similaire - AD420AN-32 |
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