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DAC3154IRGCR Fiches technique(PDF) 7 Page - Pan Jit International Inc.

No de pièce DAC3154IRGCR
Description  Dual 12-/10-Bit 500 MSPS Digital-to-Analog Converters
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Fabricant  PANJIT [Pan Jit International Inc.]
Site Internet  http://www.panjit.com.tw
Logo PANJIT - Pan Jit International Inc.

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DAC3154
DAC3164
www.ti.com
SLAS960 – MAY 2013
PIN ASSIGNMENT TABLE – DAC3164 (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
DATA INTERFACE
DATA[11:0]P/N
9/10-
I
LVDS input data bits for both channels. Each positive/negative LVDS pair has an internal 100
Ω
19/20
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two
data transfers per DATACKP/N clock cycle.
22/23,
26-27-
The data format is interleaved with channel A (rising edge) and channel B falling edge.
35/36
In the default mode (reverse bus not enabled):
DATA11P/N is most significant data bit (MSB)
DATA0P/N is most significant data bit (LSB)
DATACLK[:0]P/N
24/25
I
DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge
in multiplexed output mode.
SYNCP/N
6/7
I
Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising
edge of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N.
ALIGNP/N
24/25
I
LVPECL FIFO output syncrhonization. This positive/negative pair is captured with the rising edge of
DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it
can be left unconnected.
OUTPUT/CLOCK
DACCLKP/N
1/2
I
LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
IOUTAP/N
61/60
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
full scale current source and the most positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data
input results in a 0 mA current source and the least positive voltage on the IOUTA1 pin. The IOUTA2
pin is the complement of IOUTA1.
IOUTBP/N
53/54
O
B-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
full scale current source and the most positive voltage on the IOUTB1 pin. Similarly, a 0xFFFF data
input results in a 0 mA current source and the least positive voltage on the IOUTB1 pin. The IOUTB2
pin is the complement of IOUTB1.
REFERENCE
EXTIO
58
I/O
Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling
capacitor to GND when used as reference output.
BIASJ
57
O
Full-scale output current bias. For 20 mA full-scale output current, connect a 960
Ω resistor to GND.
POWER SUPPLY
IOVDD
45
I
Supply voltage for CMOS IO’s. 1.8V – 3.3V.
CLKVDD18
3
I
1.8V clock supply
DIGVDD18
21, 28
I
1.8V digital supply. Also supplies LVDS receivers.
VDDA18
50, 64
I
Analog 1.8V supply
VDDA33
55, 56,
I
Analog 3.3V supply
59
VFUSE
8
I
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DVDD pins for normal operation.
NC
37, 38,
Not used. These pins can be left open or tied to GROUND in actual application use.
39, 40,
51, 52
62, 63
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE-
PACKAGE
ORDERING
TRANSPORT
PRODUCT
TEMPERATURE
ECO PLAN
QUANTITY
LEAD
DESIGNATOR
NUMBER
MEDIA
RANGE
DAC3154IRGCT
250
DAC3154
DAC3154IRGCR
2000
GREEN (RoHS
QFN-64
RGC
–40°C to 85°C
DAC3164IRGC25
Tape and Reel
25
and no Sb/Br)
DAC3164
DAC3164IRGCT
250
DAC3164IRGCR
2000
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright © 2013, Texas Instruments Incorporated
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