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UC2879NG4 Fiches technique(PDF) 7 Page - Texas Instruments

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No de pièce UC2879NG4
Description  PHASE SHIFT RESONANT CONTROLLER
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

UC2879NG4 Fiches technique(HTML) 7 Page - Texas Instruments

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PIN DESCRIPTIONS
Dlin
CT
1.08
RT
=
·
·
f
UC1879
UC2879
UC3879
SLUS230B – JUNE 1998 – REVISED JUNE 2007
CLKSYNC (Bi-directional Clock and Synchronization): Used as an output, CLKSYNC provides a clock signal. As
an input, this pin provides a synchronization point. Multiple UC3879s, each with their own local oscillator
frequency, may be connected together by the CLKSYNC pin, and they will synchronize to the fastest oscillator.
This pin may also be used to synchronize the UC3879 to an external clock, provided the frequency of the
external signal is higher than the frequency of the local oscillator. CLKSYNC is internally connected to an emitter
follower pull-up and a current source pull-down (300
µA typical). Therefore, an external resistor to GND can be
used to improve the CLKSYNC pin’s ability to drive capacitive loads.
COMP (Error Amplifier Output): This pin is the output of the gain stage for overall feedback control. Error
amplifier output voltage levels below 0.9 V forces zero phase shift. Since the error amplifier has a relatively low
current drive capability, the output may be overridden by driving it with a sufficiently low impedance source.
CT (Oscillator Frequency Set): After choosing RT to set the required upper end of the linear duty cycle range,
the timing capacitor (CT) value is calculated to set the oscillator frequency as follows:
Connect the timing capacitor directly between CT and GND. Use a high quality ceramic capacitor with low ESL
and ESR for best results. A minimum CT value of 200 pF insures good accuracy and less susceptibility to circuit
layout parasitics. The oscillator and PWM are designed to provide practical operation to 600 kHz.
CS (Current Sense): This pin is the non-inverting input to the two current fault comparators whose references
are set internally to fixed values of 2 V and 2.5 V. When the voltage at this pin exceeds 2 V, and the error
amplifier output voltage exceeds the voltage on the ramp input, the phase shift limiting overcurrent comparator
will limit the phase shifting on a cycle-by-cycle basis. When the voltage at this pin exceeds 2.5 V, the current
fault latch is set, the outputs are forced OFF, and a soft start cycle is initiated. If a constant voltage above 2.5 V
is applied to this pin the outputs are disabled and held low. When CS is brought below 2.5 V, the outputs will
begin switching at 0 degrees phase shift before the SS pin begins to rise. This condition will not prematurely
deliver power to the load.
DELSETA-B, DELSETC-D (Output Delay Control): The user programmed currents from these pins to GND set
the turn on delay for the corresponding output pair. This delay is introduced between the turn off of one switch
and the turn on of another in the same leg of the bridge to allow resonant switching to take place. Separate
delays are provided for the two half-bridges to accommodate differences in the resonant capacitor charging
currents.
EA– (Error Amplifier Inverting Input): This is normally connected to the voltage divider resistors which sense the
power supply output voltage level. The loop compensation components are connected between this pin and
COMP.
GND (Signal Ground): All voltages are measured with respect to GND. The timing capacitor on CT, and bypass
capacitors on VREF and VIN should be connected directly to the ground plane near GND.
OUTA – OUTD (Outputs A-D): The outputs are 100-mA totem pole output drivers optimized to drive FET driver
devices. The outputs operate as pairs with a nominal 50% duty cycle. The A-B pair is intended to drive one
half-bridge in the external power stage and is synchronized to the clock waveform. The C-D pair drives the other
half-bridge with switching phase shifted with respect to the A-B outputs.
PWRGND (Power Ground): VC should be bypassed with a ceramic capacitor from VC to the section of the
ground plane that is connected to PWRGND. Any required bulk reservoir capacitor should be connected in
parallel. PWRGND and GND should be connected at a single point near the chip to optimize noise rejection and
minimize DC voltage drops.
RAMP (Voltage Ramp): This pin is the input to the PWM comparator. Connect it to CT for voltage mode control.
For current mode control, connect RAMP to CS and also to the output of the current sense transformer circuit.
Slope compensation can be achieved by injecting a portion of the ramp voltage from CT to RAMP.
7
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